The alias ID must be defined in device tree, because
that will be used as BUS ID to Cortex M4. If the alias ID
not defined, linux kernel will automatically allocate one
ID which might not be the same number used in Cortex M4 and
Cortex M4 will not send msg to I2C controller.

So let's add BUG_ON to catch issue as earlier as possible to avoid
wasting efforts.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>

Switch to use rpmsg i2c to support android auto, because
android auto change to use rpmsg i2c.
Also add the alias node to let m4 could use it successfully, because
M4 side use the alias id as the BUSID.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>

The resources are wrongly added.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

There are differences between the output of `make savedefconfig` and the
arm64 defconfig. This happens because CONFIG_I2C_RPBUS=y depends on
CONFIG_RPMSG=y so the latter doesn't have to be explictly selected.

Fixes: b0ee196e ("MLK-20940-4 ARM64: defconfig: Add RPBUS and RPMSG config")

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Joakim Zhang <qiangqing.zhang@nxp.com>

Since CONFIG_IR_GPIO_CIR=y depends on RC_CORE we shouldn't explicitly
define CONFIG_RC_CORE=y in defconfig, otherwise it generates a
difference between the output of "make savedefconfig" and the actual
defconfig.

Fixes: 35c88640 ("MLK-20946-3: arm64: defconfig: add IR support for imx8")

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Joakim Zhang <qiangqing.zhang@nxp.com>

Cleanup the resources that not could be set SID and remove the UNUSED

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>

Update domu car dts according to android auto changes.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>

When resources are owned by M41, we need to handle that correctly in
xen.

Also drop power doamins for xen,shared gpio, xen will power up the gpio.
gpio1 is owned by M41, so we also need to check its power status in xen.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>

CM41 runs before CortexA, we should not use smmu to restrict it, because
smmu is owned by xen. Also remove MU_13/12 which is wrongly added
before.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>

reduce the time that open operation spent,
allocate the buffer when needed

Signed-off-by: ming_qian <ming.qian@nxp.com>

mode

Can't set mode like loopback,listen-only and so on due to wrong setting when
enable ISO-FD mode.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>

kernel process(with zero pid) has no mdl mapping,
skip kernel process to avoid invalid mdl access.

also remove memory barrier to avoid rcu issue.

Signed-off-by: Xianzhong <xianzhong.li@nxp.com>

The hdmi_drm_infoframe_pack() was wrongly packing the HDR metadata. It
was setting the x display primaries followed by the y display primaries.
Instead, in the specifications, each x display primary should be
followed by the corresponding y display primary.

Also, byte 8 of the frame payload was being skipped. Fixed that too.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Reported-by: Jared Hu <jared.hu@nxp.com>

change the flexspi pad settings to pull_up and drive_low to avoid
overshoot.

Signed-off-by: Han Xu <han.xu@nxp.com>

Add delay cell support for fspi to set calibrated value to DLL register
for different clock frequency.

Signed-off-by: Han Xu <han.xu@nxp.com>

After fix the ADMA length mismatch issue on imx8mm, we can
support eMMC CMDQ, so enable it. This patch also make imx8mm
support HS400ES mode.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

After system suspend, CQE is in cqhci_off state, which set the HALT bit, make
CQE in HALT state. If the SoC do not power down the USDHC module, then when
system resume back, this bit keep the same, still set. So need to clear this
bit when enable CQE for the first request after system resume back. If not,
imx8mm will stuck in the first CMDQ request after system resume back. On
imx8qxp and imx8qm, we do not find this issue because usdhc module lost power
during system suspend/resume, and all the register return to the default reset
value, and the reset value of bit HALT is 0.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

the commit 885c943ca13d ("ENGR00288842 mmc: sdhci-esdhc-imx: add
ADMA Length Mismatch errata fix") involve the fix of ERR004536.
But double confirm with IC, need to clear the bit 7 of register
0x6c rather than set this bit 7.
here is the function of bit 7 of 0x6c:
0: enable the new IC fix for ERR004536
1: do not use the IC fix, keep the same as before

Due to the reset value of this bit 7 is 0, and ROM code also do not
touch this bit 7, so this patch directly remove the operation of this
bit 7, make sure the fix of ERR004536 can work.

Note, for all versons of 6DQP 6DQ 6DL and 6SL, IC do not has this
hardware fix, so writing this bit has no effect and we keep using
ADMA as before which has been used for several years with the
consideration of no performance drop.

For other SoC like imx6SLL imx6SX imx6UL/imx6ULL imx7 imx8, IC already
contain this hareware fix, so must make sure the bit 7 of the register
0x6c is 0. If not, we meet the ADMA length mismatch error on imx8mm-evk
and imx8qxp-ddr3l-val board when enable CMDQ.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

the data is invalid in first read for dma registers,
add second read to get the correct register data.

Signed-off-by: Xianzhong <xianzhong.li@nxp.com>

The default watchdog action is partition reset now, so no need kernel
to take care. Besides, scfw full test case may set other watchdog
action but kernel may set it back later to default partition reset
which scfw wouldn't expect, so avoid touching watchdog action.
Please modify scfw code in case changing watchdog action to board
reset.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit d9189e25)

Need to check the content protection property first in
imx_hdp_imx_encoder_enable. The function may return if
drm_hdmi_infoframe_set_hdr_metadata returns an error. This was preventing
iMX8QM from enabling content protection.

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>

Add new dts and dtsi file for virtual i2c driver on i.MX8QXP and i.MX8QM
board.

Merge fsl-imx8qm/8qxp-mek-m4.dts to fsl-imx8qm/8qxp-mek-rpmsg.dtsi. So
delete these two files.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>

Enable RPBUS(i2c-rpmsg-imx.c) and RPMSG functions.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>

cs42xx8 will call regcache_sync to refresh its register cache. However,
it will send a long msg which length is greater than the max buffer size
of virtual i2c driver. It will cause the regcache_sync operation failed.
So, use the single read/write to send i2c msg in regcache functions.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>

For the virtual i2c driver should be initialized in subsystem before the
other modules initialize. So, the imx_rpmsg and virtio_rpmsg_bus should
be initialized before virtual i2c driver. Now, use arch_initcall to
initialize these two modules.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>

Add virtual i2c driver to send SRTM i2c messages to M4.
Each virtual I2C bus has a specal bus id, which is abstracted by M4.
Each SRTM message include a bus id for the bus which the device is on.

Virtual i2c rpmsg bus will bind rpbus nodes with compatible string
"fsl,i2c-rpbus". And "rpmsg-i2c-channel" will probe only one rpmsg
channel for all rpbuses.

This virtual i2c driver depends on CONFIG_I2C and CONFIG_RPMSG.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>

IR uses GPIO1_13 not GPIO_12 in imx8mm-evk board.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>

Some test cases need to use RTC driver data, so do NOT
overwrite it using rpmsg data structure.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>

When do dpu blit and wait to finish, it will call usleep_range(10, 20)
to poll register state. Change to usleep_range(30, 50) to low down CPU loading.

Change-Id: If84c436b31d228b8b7a2a41e89611d354270baba
Signed-off-by: Ivan.liu <xiaowen.liu@nxp.com>

When system enters VLPS/VLLS mode, the IOMUXC config register
for MMDC related IO pads need to set to '0' to reduce the current
leakage for these IO pads.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>

Audio PLL is a frac pll, the config for this PLL should follow
below limitation:
    Fout = ((m + k / 65536) * FIN) / (p * 2^s),
    Fvco = ((m + k / 65536) * FIN) / p
    Fref = FIN / p

    a). 6MHz <= Fref <= 25MHz;
    b). 1 <= p <= 63;
    c). 64 <= m <= 1023;
    d). 0 <= s <= 6;
    e). -32768 <= k <= 32767;

due to the frac part calculation deviation, frac pll 'recalc_rate'
is updated to look up the pll rate from table first.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>

Set IR built-in on imx8 boards.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>

Enable IR on imx8mq-evk board.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>

Enable IR on imx8mm-evk board.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>

The following commit:

459a5fac - MLK-20263: drm/imx/dcss: fix channel-0 line shift

removed the 5 tap filter for vertical luma/chroma when YUV formats were
used.

Problem is that when the 7 tap filter is used for vertical luma/chroma,
artifacts can be seen on screen when scaling.

RGB can, however, function correctly with only 7 tap filter.

This patch partially reverts the above patch and also does some cosmetic
changes when calling the dcss_scaler_filter_design() using false/true
instead of 0/1 for use_5_taps argument.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>

Changing dev_info() to dev_dbg() has exposed an issue with the format
string, which is not constant - and leads to compilation failure in case
CONFIG_DYNAMIC_DEBUG=y:

In file included from ./include/linux/printk.h:334:0,
                 from ./include/linux/kernel.h:14,
                 from drivers/crypto/caam/compat.h:9,
                 from drivers/crypto/caam/sm_test.c:23:
drivers/crypto/caam/sm_test.c: In function 'key_display':
./include/linux/dynamic_debug.h:75:16: error: initializer element is not constant
  static struct _ddebug  __aligned(8)   \
                ^
./include/linux/dynamic_debug.h:111:2: note: in expansion of macro 'DEFINE_DYNAMIC_DEBUG_METADATA_KEY'
  DEFINE_DYNAMIC_DEBUG_METADATA_KEY(name, fmt, 0, 0)
  ^
./include/linux/dynamic_debug.h:133:2: note: in expansion of macro 'DEFINE_DYNAMIC_DEBUG_METADATA'
  DEFINE_DYNAMIC_DEBUG_METADATA(descriptor, fmt);  \
  ^
./include/linux/device.h:1351:2: note: in expansion of macro 'dynamic_dev_dbg'
  dynamic_dev_dbg(dev, format, ##__VA_ARGS__); \
  ^
drivers/crypto/caam/sm_test.c:77:2: note: in expansion of macro 'dev_dbg'
  dev_dbg(dev, label);
  ^
./include/linux/dynamic_debug.h:75:16: error: (near initialization for 'descriptor.format')
  static struct _ddebug  __aligned(8)   \
                ^
./include/linux/dynamic_debug.h:111:2: note: in expansion of macro 'DEFINE_DYNAMIC_DEBUG_METADATA_KEY'
  DEFINE_DYNAMIC_DEBUG_METADATA_KEY(name, fmt, 0, 0)
  ^
./include/linux/dynamic_debug.h:133:2: note: in expansion of macro 'DEFINE_DYNAMIC_DEBUG_METADATA'
  DEFINE_DYNAMIC_DEBUG_METADATA(descriptor, fmt);  \
  ^
./include/linux/device.h:1351:2: note: in expansion of macro 'dynamic_dev_dbg'
  dynamic_dev_dbg(dev, format, ##__VA_ARGS__); \
  ^
drivers/crypto/caam/sm_test.c:77:2: note: in expansion of macro 'dev_dbg'
  dev_dbg(dev, label);
  ^
make[3]: *** [drivers/crypto/caam/sm_test.o] Error 1

Fixes: c59d342d ("crypto: caam - lower SM test verbosity")
Suggested-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>

i.MX8QXP has separated irq, and shared irq for lpuart with eDMA,
it is better for uart to use separated irq although there has
no function impact.

Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>

Unlock hw_lock before calling v4l2_m2m_job_finish to avoid deadlock:
v4l2_m2m_job_finish -> v4l2_m2m_try_schedule -> job_ready locks hw_lock
v4l2_m2m_job_finish -> v4l2_m2m_try_run -> device_run locks hw_lock

Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>

Let's use dev_dbg() instead of dev_info() to minimize verbosity in case
we're not interested in low-level details.

While here, replace dev_info() with dev_err() in places where errors are
reported.

Reported-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>

Add the speeding grading fuse check to limit the highest speed
of cpu. fuse bits value define as below:
    speed_grading bits[1:0]        freq(MHz)
        0x0                          800
        0x1                          1000
        0x2                          1300
        0x3                          1500

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>