MA-14109 Change usleep time to low down CPU loading for DPU blit engine.

When do dpu blit and wait to finish, it will call usleep_range(10, 20)
to poll register state. Change to usleep_range(30, 50) to low down CPU loading.

Change-Id: If84c436b31d228b8b7a2a41e89611d354270baba
Signed-off-by: Ivan.liu <xiaowen.liu@nxp.com>

drivers/gpu/imx/dpu-blit/dpu-blit.c

@@ -42,7 +42,7 @@ static void dpu_cs_wait_fifo_space(struct dpu_bliteng *dpu_be)
 {
 	while ((dpu_be_read(dpu_be, CMDSEQ_STATUS) &
 		CMDSEQ_STATUS_FIFOSPACE_MASK) < CMDSEQ_FIFO_SPACE_THRESHOLD)
-		usleep_range(10, 20);
+		usleep_range(30, 50);
 }
 
 static void dpu_cs_wait_idle(struct dpu_bliteng *dpu_be)
@@ -243,7 +243,7 @@ void dpu_be_wait(struct dpu_bliteng *dpu_be)
 
 	while ((dpu_be_read(dpu_be, COMCTRL_INTERRUPTSTATUS0) &
 		STORE9_SEQCOMPLETE_IRQ_MASK) == 0)
-		usleep_range(10, 20);
+		usleep_range(30, 50);
 
 	dpu_be_write(dpu_be, STORE9_SEQCOMPLETE_IRQ_MASK,
 		COMCTRL_INTERRUPTCLEAR0);