It turns out the following display modes are not well supported
by the bridge - 1600x900@60, 1280x1024@60, 1280x720@30/25/24
and 1152x864@75.  Fortunately, they are not that widely used.
So, list them as the known bad display modes and filter them out
in ->mode_valid().

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit c44ed03cf3b85d7f5bc8325ffeec9fd07f66aa87)
(cherry picked from commit 20e29dd9)

There are some issues with the HDMI connection on it6263 being slow to
come up. There is a hack there which reads the register multiple times
but it doesn't seem to be sufficient. This is particularly a problem
when inside a xen guest.

Improve this workaround by reading the status multiple times every few
5-10ms and returning connector_status_connected if any of those reads
sees HPDETECT.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 699ccad2)

When CONFIG_OF_DYNAMIC is used, and this driver is enabled in
devicetree, but fails to probe a physical i2c client, it should disable
it's remote endpoint, so that the DRM master device won't fail to bind
the other available devices.
Usually, the remote endpoint of this device is a DRM encoder. If a DRM
encoder fails to bind, the DRM master device will also fail to bind.
This is why, we should disable the encoder node dynamically in
devicetree.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit de618474)

This addresses a problem with colors that are sometimes incorrect after
startup. Now the AVI packet is initialized with RGB color space rather
than relying on the default.

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
(cherry picked from commit c1f73434)

We call the helper drm_detect_hdmi_monitor() to check if the EDID blob read
from a monitor indicates the monitor is connected via HDMI or not.  We pass
an edid structure to the helper.  However, the structure has been freed
before we use it.  This patch moves the helper up before the structure is
freed to fix the issue.

Fixes: a5c01aa91842 ("MLK-15001-25 drm/bridge: Add ITE IT6263 LVDS to HDMI transmitter support")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 3522359b)

There is cable detection failure issue on i.MX8qxp MEK platform at boot
time when we use single LVDS to HDMI display.  The workaround is to read
the cable detection status for even more times.  Based on experiments, it
looks reading for 90 times works.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 5ac4dfb7)

A low pulse whose width is at least 40ms on pin SYSRSTN
may reset the bridge, according to the chip maker.
This patch adds gpio reset support for the bridge.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 2e120abc)

There is cable detection failure issue on i.MX8qxp arm2 platform
at boot time when we avoid imx-drm deferral probe entirely(i2c
bus driver probe needs to be before the it6263 driver probe).
The workaround is to read the cable detection status multiple
times.  Based on experiments, it looks reading for 40 times works.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit fb719c95)

This patch adds IT6263 video support.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit bf1acefa)

s/in pratical/in practice

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 15bcff90)

The JDI TX26D202VM0BWA panel works in data enable(DE) mode.
Apparently, the panel's data enable signal is active high
according to the panel spec.  This patch corrects the DE
signal polarity from active low to active high.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit ed0230ec)

This patch adds support for Japan Display Inc. 10.1" TX26D202VM0BWA
WUXGA(1920x1200) TFT LCD panel with LVDS interface.
The panel has dual LVDS channels.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 6e097872)

When the master imx-drm-core binding fails, component_bind_all()
in imx-drm-core ->bind() callback will unbind all bound components
first and then call drm_mode_config_cleanup().  Since the encoder
and connector(located in imx_ldb.imx_ldb_channel) are freed after
the ldb ->unbind() callback, drm_mode_config_cleanup() would
accidentally access the freed encoder and connector again.  To fix
this issue, we should cleanup the encoder and connector, i.e.,
remove them from the global encoder and connector lists, in the
->unbind() callback, so that, drm_mode_config_cleanup() won't find
them again in the lists.  However, we have to make sure they exist
before the cleanup in the ->unbind() callback, because imx-drm-core
->unbind() calls drm_mode_config_cleanup() first and then unbinds
all components via component_unbind_all().  Moreover, the connector
isn't created at the first place if a bridge exists, so the check
before the cleanup makes sense for this reason as well.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit a39bb207)

The return value of sc_misc_set_control() should be checked in
ldb_pixel_link_init(), instead of being ignored.  This patch
fixes this issue.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 7c902e39)

Unlike i.MX6qdl and i.MX53 LDB variants, the i.MX8 LDB variants(i.MX8qxp
and i.MX8qm) in existence don't have frontend mux, thus, we should split
the logic to program the ch0/1_mode for variants w/wo the mux.  It turns
out LDB_CH0_MODE_EN_TO_DI0 can be used for channel0 in both LDB single
mode and LDB split mode for the i.MX8 LDB variants.  However, based on
test results, for i.MX8qm LDB channel1, LDB_CH1_MODE_EN_TO_DI1 has to be
used in single mode, while, i.MX8qxp may work with LDB_CH1_MODE_EN_TO_DI0
or LDB_CH1_MODE_EN_TO_DI1.  With LDB_CH1_MODE_EN_TO_DI0, i.MX8qm LDB
channel1 would output wrong image in single mode(it looks like color
is wrong based on test results).  The i.MX8 LDB variants channel1 mode
can still be LDB_CH1_MODE_EN_TO_DI0 in split mode(the patch doesn't
touch this).  In essence, this patch fixes the channel1 single mode for
i.MX8qm LDB by correcting the ch1_mode, while all other features
should work as before.  Note that due to hardware issue, we didn't test
the channel1 single mode for i.MX8qm.  We need to populate several
resistors to enable the connectors driven by channel1 in single mode
for either ARM2 platform or MEK board.  Tests are done with IT6263
LVDS to HDMI transmitter driven by LDB0 channel1 after r206, r207, r208
and r209 are populated on the i.MX8qm MEK board.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit d9b35ed0)

i.MX8dx/dxp/qxp use two LDBs(one primary, one auxiliary) to support
dual channel mode.  This patch adds the dual channel mode support
for i.MX8dx/dxp/qxp.  Note that the drivers contain specific sequence
needed by this mode - LDB VSYNC polarity and channel selection settings
should be configured into the register a bit earlier in ->atomic_mode_set
instead of in ->enable, and DC subsystem pixel link enablement is moved
from the DPU driver to the LDB driver to make sure it happens later
than LDB clocks enablement in ->enable.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 3b6fc6c9)

i.MX8qxp uses two LDB(one primary, one auxiliary) to support dual
channel mode.  This patch adds DT property descriptions for those
properties needed by this case.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit d07d63c1)

When an external display device works in data enable(DE) mode,
it usually provides video mode(s) without HSYNC and VSYNC
polarities via display flags.  In this case, the controller(LDB)
and the LVDS PHY still need to align the two signal polarities
with each other respectively.  Otherwise, polarities generated
by default register values may cause mismatch polarities and
display artifacts.  With the DE mode JDI TX26D202VM0BWA panel,
we see vertical lines(very likely, only one) at the left boundary
are missing sometimes, which is caused by this mismatch.  This
patch replaces the default polarity status with explicit active
high in DE mode to fix the issue.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 69f6ca59)

The system power management operations should get correct driver data
before going on to further handling.  When the component is unbinded,
driver data should be set to NULL so that the system power management
may be bypassed(return early).  This way, we may prevent the system power
management from using any invalid driver data.

Fixes: 915ac0ad7369 ("MLK-16581-7 drm/imx: ldb: Add system power management support")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 91033d87)

This patch adds system power management support for imx-ldb drm driver
by proper PHY power/exit/init handling where necessary and pixel link
re-initialization in the resume operation.  The driver depends on the
imx-drm core driver to handle ldb bridge power management operations.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 1e83202a)

Due to i.MX8 clock issue, we need to get bypass and pixel clock rates
before setting their rates when system resumes back from PM sleep mode,
otherwise, we'll fail to set the clock rates.  So, this is a workaround
and it can be removed when the clock issue is properly fixed.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 17b68807)

In dual mode, we return too early from ->bind when we get
the auxiliary channel's PHY.  This causes we miss the logics
to set driver data, get ldb alias id and initialize pixel
link(if necessary).  This patch fixes the issue here by
tweaking the driver logic to do component binding properly.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 94bf9cef)

To enable or disable a display safely, we need to validate pixel link
after the relevant ldb channel is enabled and invalidate pixel link
before the channel is disabled.  These operations are recommended
by the design team.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 5fab9a74)

This patch specifies the existing pixel link quirks is initialization related.
This may help us distinguish between the pixel link quirks and another one
up-coming which is validation and invalidation related.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 8433571e)

This code is enabled in upstream imx_v6_v7_defconfig but fails to build
because of sc api calls. Fix this by adding ifdef checks to pixel_link
code.

Check for CONFIG_HAVE_IMX8_SOC becuase it is selected by both 8qm and
8qx.

These calls are already guarded at runtime with checks for devtype
pixel_link_valid_quirks so the empty ifdefed functions will never get
called anyway.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>

It might make sense to add a dedicated config option for SC api
like CONFIG_HAVE_IMX_SCU, right now drivers/soc/imx/sc is guarded by
CONFIG_ARCH_FSL_IMX8QM which means you can't build 8qxp separately.

(cherry picked from commit a928239d)

This patch adds i.MX8qxp LDB support.
Logics are added to make i.MX8qxp LDB cope with Mixel LVDS combo PHY.
Also, logics are added to handle pixel link quirks for i.MX8qxp LDB.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 086248a0)

This patch adds i.MX8qm LDB support.
Logics are added to make i.MX8qm LDB cope with Mixel LVDS PHY.
Also, logics are added to handle pixel link padding quirks for i.MX8qm LDB.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit d8e089c7)

This reverts commit a43eac2d.
This patch break the i.MX8, revert it firstly.

(cherry picked from commit a1bfd5b6)

Due to i.MX8 clock issue, we need to get PHY clock rate
before setting it's rate when system resumes back from
PM sleep mode, otherwise, we'll fail to set the clock rate.
So, this is a workaround and it can be removed when
the clock issue is properly fixed.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit fca3d4b1)

Due to i.MX8 clock issue, we need to get PHY clock rate
before setting it's rate when system resumes back from
PM sleep mode, otherwise, we'll fail to set the clock rate.
So, this is a workaround and it can be removed when
the clock issue is properly fixed.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit f9709fbf)

Fast-forward dpu KMS driver from imx_4.14.y.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

Fast-forward dpu common driver from imx_4.14.y.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

Fast-forward imx8_pc driver from imx_4.14.y.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

Fast-forward imx8_dprc driver from imx_4.14.y.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

Fast-forward imx8_prg driver from imx_4.14.y.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

On recent kernels clks which are marked with CLK_SET_RATE_GATE are
"protected" against further changes at clk_prepare time. This
clk_core_rate_protect propagates up the clk tree and causes cpufreq
switches to fail later on.

See drivers/clk/clk.c around line 770.

Fix this by removing the CLK_SET_RATE_GATE flag for this specific clk.
This is safe because a53 clks are always only manipulated through
cpufreq.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>

CID 17797 and 3275140: fix potential null pointer dereferencing.

Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>

Fix coverity CID 17388, 17389 and 17363 issue
Because the type of variable is unsigned, so compare with zero is no
effect

Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>

When any fail happens during master's '>bind()' function, the
drm_device' pointer data which is set to the device driver data
will be put and freed. But if later, system suspend is called,
the freed 'drm_device' pointer will be used again.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>

For syncing with unstreaming kernel on UART driver from 4.19 changed
to rom script for uart rx path, and the compatiblity of legacy kernel
using ram script, add both uart rom and ram script support, so add
rom script address.

ram script:
	uart_2_mcu_fix_addr
	uartsh_2_mcu_fix_addr /* through spba bus */
rom script:
	uart_2_mcu_addr
	uartsh_2_mcu_addr /* through spba bus */

Signed-off-by: Robin Gong <yibin.gong@nxp.com>