MLK-21378-2 gpu: imx: Add imx8_dprc support

Fast-forward imx8_dprc driver from imx_4.14.y.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt

@@ -250,6 +250,38 @@ prg@56040000 {
 	power-domains = <&pd_dc0>;
 };
 
+Freescale i.MX8 DPRC (Display Prefetch Resolve Channel)
+=======================================================
+Required properties:
+- compatible: should be "fsl,<chip>-dpr-channel"
+- reg: should be register base and length as documented in the
+  datasheet
+- fsl,sc-resource: SCU resource number as described in
+  Documentation/devicetree/bindings/soc/fsl/imx_rsrc.txt
+- fsl,prgs: phandles to the PRG unit(s) attached to this DPRC, the first one
+  is the primary PRG and the second one(if available) is the auxiliary PRG
+  which is used to fetch luma chunk of a YUV frame with 2 planars.
+- clocks: phandles to the DPRC apb, b and rtram clocks, as described in
+  Documentation/devicetree/bindings/clock/clock-bindings.txt,
+  Documentation/devicetree/bindings/clock/imx8qm-clock.txt and
+  Documentation/devicetree/bindings/clock/imx8qxp-clock.txt
+- clock-names: should be "apb", "b" and "rtram"
+- power-domains: phandle pointing to power domain
+
+example:
+
+dpr-channel@56100000 {
+	compatible = "fsl,imx8qm-dpr-channel";
+	reg = <0x0 0x56100000 0x0 0x10000>;
+	fsl,sc-resource = <SC_R_DC_0_VIDEO0>;
+	fsl,prgs = <&prg4>, <&prg5>;
+	clocks = <&clk IMX8QM_DC0_DPR1_APB_CLK>,
+		 <&clk IMX8QM_DC0_DPR1_B_CLK>,
+		 <&clk IMX8QM_DC0_RTRAM1_CLK>;
+	clock-names = "apb", "b", "rtram";
+	power-domains = <&pd_dc0>;
+};
+
 Parallel display support
 ========================
 

drivers/gpu/imx/Kconfig

@@ -3,6 +3,11 @@ config IMX8_PRG
 	default y if IMX_DPU_CORE=y
 	default m if IMX_DPU_CORE=m
 
+config IMX8_DPRC
+	tristate
+	default y if IMX_DPU_CORE=y
+	default m if IMX_DPU_CORE=m
+
 source drivers/gpu/imx/ipu-v3/Kconfig
 source drivers/gpu/imx/lcdif/Kconfig
 source drivers/gpu/imx/dcss/Kconfig

drivers/gpu/imx/Makefile

 obj-$(CONFIG_IMX8_PRG)	+= imx8_prg.o
+obj-$(CONFIG_IMX8_DPRC)	+= imx8_dprc.o
 
 obj-$(CONFIG_IMX_IPUV3_CORE)	+= ipu-v3/
 obj-$(CONFIG_IMX_LCDIF_CORE)	+= lcdif/

include/video/imx8-prefetch.h

@@ -47,4 +47,28 @@ void prg_set_auxiliary(struct prg *prg);
 void prg_set_primary(struct prg *prg);
 void prg_set_blit(struct prg *prg);
 
+struct dprc;
+struct dprc *
+dprc_lookup_by_phandle(struct device *dev, const char *name, int index);
+void dprc_enable(struct dprc *dprc);
+void dprc_disable(struct dprc *dprc);
+void dprc_configure(struct dprc *dprc, unsigned int stream_id,
+		    unsigned int width, unsigned int height,
+		    unsigned int x_offset, unsigned int y_offset,
+		    unsigned int stride, u32 format, u64 modifier,
+		    unsigned long baddr, unsigned long uv_baddr,
+		    bool start, bool aux_start, bool interlace_frame);
+void dprc_reg_update(struct dprc *dprc);
+void dprc_first_frame_handle(struct dprc *dprc);
+void dprc_irq_handle(struct dprc *dprc);
+void dprc_enable_ctrl_done_irq(struct dprc *dprc);
+bool dprc_format_supported(struct dprc *dprc, u32 format, u64 modifier);
+bool dprc_stride_supported(struct dprc *dprc,
+			   unsigned int stride, unsigned int uv_stride,
+			   unsigned int width, u32 format);
+bool dprc_stride_double_check(struct dprc *dprc,
+			      unsigned int width, unsigned int x_offset,
+			      u32 format, u64 modifier,
+			      dma_addr_t baddr, dma_addr_t uv_baddr);
+
 #endif