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  1. May 23, 2022
  2. May 20, 2022
  3. May 19, 2022
  4. May 18, 2022
  5. May 17, 2022
    • Gagandeep Singh's avatar
      LF-5955: arm64: dts: ls1028a-rdb-dpdk: use SGMII in-band AN for eno0 · 463f7442
      Gagandeep Singh authored
      
      Due to ERR050089 (MDIO register issue), Linux may not access the MDIO
      controller concurrently with DPDK accessing an ENETC PF or VF.
      
      If the user assigns all ports to DPDK via vfio-pci, DPDK could rely on PHY
      initialization performed by Linux. But since the user is free to assign
      only a subset of ENETC ports to DPDK, this means that when DPDK is
      expected to run, Linux cannot be allowed to access the MDIO controller
      at all.
      
      Therefore, the DPDK device tree relies on PHY initialization done by the
      bootloader.
      
      However, Linux probes the ENETC ports, performs a PCIe FLR and this
      changes PCS settings. Therefore, while DPDK inherits PHY initialization
      from U-Boot, it inherits PCS initialization from Linux.
      
      Prior to commit 71b77a7a ("enetc: Migrate to PHYLINK and PCS_LYNX"),
      the driver used to enable in-band autoneg in the PCS unconditionally.
      Whereas with phylink support, in-band autoneg is enabled when
      'managed = "in-band-status"' is present, disabled otherwise. For
      traffic to pass, the in-band setting on the PCS must be kept in sync
      with the in-band setting on the PHY, and that means we must keep the
      "in-band-status" property.
      
      However, it is illegal to have both a "managed" and a "fixed-link" stanza,
      because phylink errors out:
      
      [    8.368016] fsl_enetc 0000:00:00.0: enabling device (0400 -> 0402)
      [    8.378604] fsl_enetc 0000:00:00.0: can't use both fixed-link and
      		in-band-status
      [    8.396208] fsl_enetc: probe of 0000:00:00.0 failed with error -22
      
      The DPDK device tree avoided this issue by deleting the
      "phy-connection-type" property, which made the Linux driver operate in a
      "PHY-less PF" mode where it did not register with phylink at all.
      This operating mode is not actually functional, since Linux is not able
      to pass traffic using it, and recently was removed upstream.
      
      We must choose a configuration that works for both DPDK and for Linux
      (with the assumption that an initial PHY configuration was done by
      U-Boot). This is to use phylink and the Lynx PCS driver to enable in-band
      autoneg, which will automatically adapt the MAC link speed to what was
      negotiated on the copper side by the Atheros PHY (which is invisible to
      Linux). This operating mode is identical to what we do for Felix switch
      ports when DPDK is in use.
      
      Note that it isn't necessary to delete the MDIO bus per se, as long as no
      Ethernet port is connected to a PHY on this bus. MDIO reads are initiated
      at runtime only by the PHY library, and the PHY library only runs when
      initiated by an Ethernet port.
      
      Signed-off-by: default avatarGagandeep Singh <g.singh@nxp.com>
      Reviewed-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: default avatarLi Yang <leoyang.li@nxp.com>
      463f7442
  6. May 16, 2022
  7. May 13, 2022
  8. May 12, 2022
  9. May 11, 2022
  10. May 09, 2022
    • Oliver F. Brown's avatar
      LF-6005: gpu: imx: dpu: framegen: Improve clock handling · fa0384dc
      Oliver F. Brown authored
      
      The bypass clock and display pixel clock needs to be set for HDMI.
      
      Signed-off-by: default avatarOliver F. Brown <oliver.brown@nxp.com>
      Reviewed-by: default avatarLiu Ying <victor.liu@nxp.com>
      fa0384dc
    • zhipeng.wang's avatar
      MA-19173 CONFIG_UBSAN cause kernel panic when connect camera · 424dc46e
      zhipeng.wang authored
      
      [    8.048049][  T223] Unexpected kernel BRK exception at E1
      [    8.051385][  T223] Internal error: BRK handler: f2000001 [#1]PREEMPT SMP
      [    8.287484][  T223] Call trace:
      [    8.290630][  T223]  ov5640_probe+0x854/0x858 [ov5640_camera_mipi_v2]
      [    8.297077][  T223]  i2c_device_probe+0x200/0x280
      [    8.301785][  T223]  really_probe+0x1c0/0x4a8
      [    8.306143][  T223]  driver_probe_device+0x68/0xc0
      [    8.310935][  T223]  device_driver_attach+0x70/0xb4
      [    8.315814][  T223]  __driver_attach+0xc8/0x150
      [    8.320346][  T223]  bus_for_each_dev+0x84/0xd4
      [    8.324878][  T223]  driver_attach+0x28/0x38
      [    8.329149][  T223]  bus_add_driver+0x108/0x1e8
      [    8.333681][  T223]  driver_register+0x7c/0x118
      [    8.338214][  T223]  i2c_register_driver+0x48/0xa4
      [    8.343010][  T223]  init_module+0x24/0xfe8 [ov5640_camera_mipi_v2]
      [    8.349280][  T223]  do_one_initcall+0xec/0x318
      [    8.353814][  T223]  do_init_module+0x60/0x3a0
      [    8.358262][  T223]  load_module+0x2ad0/0x3248
      [    8.362708][  T223]  __arm64_sys_finit_module+0xbc/0xfc
      [    8.367935][  T223]  el0_svc_common+0xa4/0x180
      [    8.372380][  T223]  do_el0_svc+0x28/0x7c
      [    8.376392][  T223]  el0_svc+0x14/0x24
      [    8.380142][  T223]  el0_sync_handler+0x6c/0xb4
      [    8.384673][  T223]  el0_sync+0x19c/0x1c0
      
      UBSAN is a runtime undefined behaviour checker.
      
      Array ov5640_mode_info_data[2][5], and the value of mode and orig_mode
      may be 0xff, so there is an undefined access problem.
      
      Change-Id: I9e3487fa2fe2543e37018c494a159345b5ab991e
      Signed-off-by: default avatarzhipeng.wang <zhipeng.wang_1@nxp.com>
      (cherry picked from commit 5040dffc9e38255f8bedc9483e58989b6077fc2a)
      424dc46e
    • Ming Qian's avatar
      LF-5445: media: imx-jpeg: Add pm-sleep support for imx-jpeg · 63c92d71
      Ming Qian authored
      
      Wait finishing jpeg job before system sleep,
      otherwise the encoding/decoding can't be resumed after suspend.
      
      Signed-off-by: default avatarMing Qian <ming.qian@nxp.com>
      Reviewed-by: default avatarMirela Rabulea <mirela.rabulea@nxp.com>
      63c92d71
    • Haibo Chen's avatar
      LF-6013 gpio: gpio-vf610: do not touch other bits when set the target bit · 6b1d525b
      Haibo Chen authored
      
      For gpio controller contain register PDDR, when set one target bit,
      current logic will clear all other bits, this is wrong. Use operator
      '|=' to fix it.
      
      Reviewed-by: default avatarClark Wang <xiaoning.wang@nxp.com>
      Signed-off-by: default avatarHaibo Chen <haibo.chen@nxp.com>
      6b1d525b
  11. May 06, 2022
  12. May 04, 2022
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