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Integrate u-boot-seco-imx/seco_lf_v2021.04_d18-video

GitBot requested to merge u-boot-seco-imx/seco_lf_v2021.04_d18-video into kirkstone

Commit: edgehog/bsp/nxp/u-boot-seco-imx@8e7576e0

[D18][BOARD] setup U-Boot video environment

Depending on the board straps, setup the correct video link.

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Commit: edgehog/bsp/nxp/u-boot-seco-imx@558a4c9b

[D18][DTS] add eDP video support

  • on CSB79REVB: panel BOE EV156FHM (eDP0 CN60: switch SW6 2-4 position ON, jumper CN18 and CN19 position 1-2)

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Commit: edgehog/bsp/nxp/u-boot-seco-imx@b68f7eab

[D18][BOARD] set eDP BRG enable

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Commit: edgehog/bsp/nxp/u-boot-seco-imx@62414408

[D18][DEFCONFIG] add eDP display support

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Commit: edgehog/bsp/nxp/u-boot-seco-imx@0677ded8

[DRIVER] video: add TI SN65DSI86 DSI to eDP bridge driver

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Commit: edgehog/bsp/nxp/u-boot-seco-imx@d19e33e9

[D18][ENV] set SPLASHIMAGE_ADDR

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Commit: edgehog/bsp/nxp/u-boot-seco-imx@58b5d692

[D18][DTS] add LVDS FHD dual-channel video support

  • on CSB79REVB: panel AUO P215HVN01.0 + CV1235/750REVB (LVDS CN14: switch SW6 1-3 and 2-4 position OFF, jumper CN18 position 2-3 and CN19 position 1-2)

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Commit: edgehog/bsp/nxp/u-boot-seco-imx@e5732d31

[D18][BOARD] set LCD0 VDD, BKL enable

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Commit: edgehog/bsp/nxp/u-boot-seco-imx@3a7a80f0

[D18][DEFCONFIG] add LVDS display support

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Commit: edgehog/bsp/nxp/u-boot-seco-imx@2e2c523f

[D18][BOARD] fix pad mux configuration

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Commit: edgehog/bsp/nxp/u-boot-seco-imx@651db7e4

[D18][DTS] clear reference board peripherals

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Commit: edgehog/bsp/nxp/u-boot-seco-imx@55915d79

[i.MX8MP][DRIVER] configure display clk tree

  • add frequency 1039.5M to pll1443x table
  • set VIDEO_PLL to 1039.5M
  • set AXI_CLK to 500M from SYSTEM_PLL2
  • set MIPI_PHY1_REF_CLK to 12M from OSC_24M (for dsi)
  • set LDB_CLK to 519.75M from VIDEO_PLL (for lvds)
  • configure clk tree differently depending on display:
    • lcdif1 (for dsi): set DISP1_PIX_CLK from VIDEO_PLL
    • lcdif2 (for lvds): set DISP2_CLK from VIDEO_PLL

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Commit: edgehog/bsp/nxp/u-boot-seco-imx@3e66940d

[i.MX8MP][D18][DTS] add i.MX8MP LVDS nodes

REFERENCE: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Add-i-MX8MP-LVDS-driver-in-uboot/ta-p/1434826

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Commit: edgehog/bsp/nxp/u-boot-seco-imx@2f1d076c

[DRIVER] video: imx: add i.MX8MP LVDS bridge driver

REFERENCE: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Add-i-MX8MP-LVDS-driver-in-uboot/ta-p/1434826

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Commit: edgehog/bsp/nxp/u-boot-seco-imx@3bf38367

LFU-247-2 video: sec_dsim: Update DPHY PLL PMS and DPHY timing settings

Change to calculate the PLL PMS at runtime for bit_clk, not use hardcode value for 1080p@60 only.

Also update the DPHY timing settings to follow kernel to select values from a pre-setting table.

Signed-off-by: Ye Li ye.li@nxp.com Reviewed-by: Peng Fan peng.fan@nxp.com (cherry picked from commit a2ca81dc77f1e79e4fe6a0369b9f702b2829e8be)

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Commit: edgehog/bsp/nxp/u-boot-seco-imx@b6cf563e

LFU-247-1 imx8m: clock: Add function to get DSI PHY reference clock rate

The D-PHY ref clock source is configurable. We need to know the reference clock rate for D-PHY PLL calculation.

Signed-off-by: Ye Li ye.li@nxp.com Reviewed-by: Peng Fan peng.fan@nxp.com (cherry picked from commit 2560cd096e54d21d5b68fd3cb70e4d3140854bc3)

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