LFU-247-2 video: sec_dsim: Update DPHY PLL PMS and DPHY timing settings

Change to calculate the PLL PMS at runtime for bit_clk, not use
hardcode value for 1080p@60 only.

Also update the DPHY timing settings to follow kernel to select values
from a pre-setting table.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit a2ca81dc)

drivers/video/nxp/imx/sec_dsim_imx.c

@@ -24,9 +24,6 @@
 #include <regmap.h>
 #include <syscon.h>
 
-/* fixed phy ref clk rate */
-#define PHY_REF_CLK		27000000
-
 struct imx_sec_dsim_priv {
 	struct mipi_dsi_device device;
 	void __iomem *base;