Add first .gitlab-ci.yml file with build job. Changed
image and toolchain path to compile for kernel 5.10

built-in

This driver coming from SECO driver library:
    - driver: seco_pwm_generic
    - version: v1.0

    This driver provides a SYSFS interface for a PWM controller.

Add LPC tty device: /dev/lpctty#

    This driver coming from SECO driver library:
    - driver: seco_clk_consumer
    - version: v1.0

    This driver provides a SYSFS interface for a variable CLK.

This add-on regards the eight PWMs prensent into the LSIO part of the processor. This is due to the fact that in this version of kernel NXP has not included the nodes about these PWMs.
As reference the past kernel 4.19 (SECO internal) has been used.

Now it is possible to enable and use a pwm# node into dts of out boards.

This driver coming from SECO driver library:
- driver: seco_pwr_btn
- version: v1.0

This driver manage a GPIO (e.g. a pwr button signal) and its pressure
event. This event rise up to user space level, via a user space event
with literal name "Embedded Controller - power_button"

This driver coming from SECO driver library:
- driver: seco_cpld_imx6
- version: v1.0

This driver is generic but is used only by [i.MX6][928].
The WEIM bus is used to communicate with the CPLD.
There are two CPLD's versions:
- LPC bridge: a LPC bridge is implemented and the actual drivers
  compatible with this bus are:
	- sio_xr28v382: support for MaxLinear XR28V382 with x2 UARTs
	- sio_w83627: support for Nuvoton W83627 superIO
- GPIO x8 + PWM: a GPIO expander plus a PWM controller are present into
  CPLD. In this case the driver are cgpio_expander.c and pwm_cpld.c
  respectively.
The serial_core of the kernel has been modified inorder to support the
specific UART type coming from LPC compatible driver.
Since, as mentioned, this driver is used only by the [928] module,
please, refer to its dts file about the device-tree, where there is the
hierarchy:

WEIM
 |__ CPLD
     |__ GPIO + PWM
     |__ LPC
          |__ XR28V382
          |__ W83627

Note: all node on the same level are mutually exclusive

The original driver does not manage WCR, one of the parameter of the WEIM bus.
Now the WCR can be set via device-tree.

it is a copy of file imx_v8_defconfig, by NXP

Made this in order to isolate all dts file of all SECO's DTS file.
All file of the silicon vendor have been confined into an include
folder.

Made this in order to isolate all dts file of all SECO's DTS file.
This is no common for arm tree of the kernel source but is common for
the arm64 tree.

all *.dts file with suffix "-overlay" into name will be managed as dtbo
file

This driver coming from SECO driver library:
- driver: goodix_gt9xx
- version: v2.1

This driver coming from SECO driver library:
- driver: seco_ectrl_msp430
- version: v1.1

Note: Acvtually this drivers is used only for SECO boards based on i.MX6
CPU since these boards are the only one that have MSP450 MCU as Embedded
Controller.

It is a copy of file imx_v7_defconfig, by NXP

Do not need to read quite large data through i2c bus, accroding to driver
logic, only need the first 8 byte data. So change this length to 9.

Add this change also can fix one error on imx8ulp-evk board, because the
touch is on rpmsg-i2c bus, rpmsg limitate the data size, can't be large
than 14 byte. If config a large data size, will trigger i2c error.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

Currently on imx8ulp-evk board, the interrupt pin we use is from M core
domain, need use gpio-rpmsg to handle the interrupt. If frequently free
or request this irq during suspend/resume, system will randomly hang.
As a workaround, just disable/enable instead.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

After we start to do core soft reset while switch to device
mode, the phy init will be done at every switch, but its counter
part de-init is missing, this cause the phy init and exit is not
balanced, then when we really need do phy init like system resume,
it will not be done by phy driver because the maintained counter
is not 0. Considering actually phy init is redundant while mode
switch, so move out the phy init to dwc3 core init where is the
only place required.

Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Tested-by: faqiang.zhu <faqiang.zhu@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

In SDIO mode, auto-tuning only support 1-bit mode as device sends
an async interrupt to uSDHC through DAT1 during interrupt period
which implies 4-bit auto tuning is not supported under SDIO mode.

Reviewed-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

The same patch "net: sched: add barrier to ensure correct
ordering for lockless qdisc" is duplicated with these
two commit ID (e7c3ae47
and 9486b3dd) in the process
of merge(commid ID: 8b0b3faf):

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>

The variable 'ext_temp' presenting the external temperature is expected to be
used when call with DEFAULT_TEMP_INDEX and overridden by new value if read out
successfully from the PMIC. For some reason sometimes the temperature value from
PMIC is not correct on MX8ULP (e.g., read out as '0'), disable it temporarily.
As a consequence, it causes the variable 'ext_temp' might be uninitialized
and then set a wrong temperature index to register.

This patch fixed this Uninitialized problem by setting to DEFAULT_TEMP.

Current logic is the driver will use DEFAULT_TEMP unless the user assigns
different value. To revisit PMIC temperature driver to restore previous logic.

Signed-off-by: Robby Cai <robby.cai@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

Fix below section mismatch build warning:

WARNING: modpost: vmlinux.o(.text+0x6b20b8): Section mismatch in reference
from the function imx8_soc_info() to the function .init.text:imx8mq_noc_init()
The function imx8_soc_info() references
the function __init imx8mq_noc_init().
This is often because imx8_soc_info lacks a __init
annotation or the annotation of imx8mq_noc_init is wrong.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

Fix below section mismatch build warning in imx8mm/mn/mq clock driver:

WARNING: modpost: vmlinux.o(.text+0x667618): Section mismatch in reference
from the function imx8mm_clocks_probe() to the function .init.text:imx_clk_init_on.isra.0()
The function imx8mm_clocks_probe() references
the function __init imx_clk_init_on.isra.0().
This is often because imx8mm_clocks_probe lacks a __init
annotation or the annotation of imx_clk_init_on.isra.0 is wrong.

WARNING: modpost: vmlinux.o(.text+0x66a034): Section mismatch in reference
from the function imx8mn_clocks_probe() to the function .init.text:imx_clk_init_on.isra.0()
The function imx8mn_clocks_probe() references
the function __init imx_clk_init_on.isra.0().
This is often because imx8mn_clocks_probe lacks a __init
annotation or the annotation of imx_clk_init_on.isra.0 is wrong.

WARNING: modpost: vmlinux.o(.text+0x6713f8): Section mismatch in reference
from the function imx8mq_clocks_probe() to the function .init.text:imx_clk_init_on.isra.0()
The function imx8mq_clocks_probe() references
the function __init imx_clk_init_on.isra.0().
This is often because imx8mq_clocks_probe lacks a __init
annotation or the annotation of imx_clk_init_on.isra.0 is wrong.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

For i.MX8MN DDR3L EVK board, it uses a 11x11 package that VDD_ARM & VDD_SOC
is combined together, the 'cpu-supply' should be buck1, so correct it.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

Enable configs for AF_ALG socket based interface to Kernel cryptography
CONFIG_CRYPTO_USER_API_HASH
CONFIG_CRYPTO_USER_API_SKCIPHER
CONFIG_CRYPTO_USER_API_AEAD

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Varun Sethi <v.sethi@nxp.com>
Reviewed-by: Silvano Di Ninno <silvano.dininno@nxp.com>

update base_bd_ptr for channel0 after bd0 descriptor allocated again.
Otherwise, sdma may hang if the stale/wrong bd0 data touched by channel0
as below:

[  221.334360] imx-sdma 30e10000.dma-controller: Timeout waiting for CH0 ready
[  221.341333] imx-sdma 30e10000.dma-controller: save context error!
[  221.347437] PM: dpm_run_callback(): sdma_suspend+0x0/0x160 returns -110
[  221.354054] PM: Device 30e10000.dma-controller failed to suspend late: error -110
[  221.361937] PM: late suspend of devices failed
[  221.370127] ------------[ cut here ]------------
[  221.374745] lcdif_pixel_clk already disabled
[  221.379050] WARNING: CPU: 0 PID: 4510 at drivers/clk/clk.c:952 clk_core_disable+0xa4/0xb0
[  221.387222] Modules linked in: snvs_ui(O) fsl_jr_uio caam_jr caamkeyblob_desc caamhash_desc caamalg_desc crypto_engine rng_core authenc libdes crct10dif_ce imx8_media_dev(C) flexcan can_dev caam secvio error fuse [last unloaded: snvs_ui]
[  221.408283] CPU: 0 PID: 4510 Comm: rtc_wakeup.sh Tainted: G         C O      5.10.52-lts-5.10.y+g5788c4507376 #1
[  221.418451] Hardware name: NXP i.MX8MPlus EVK board (DT)
[  221.423761] pstate: 40000085 (nZcv daIf -PAN -UAO -TCO BTYPE=--)
[  221.429764] pc : clk_core_disable+0xa4/0xb0
[  221.433943] lr : clk_core_disable+0xa4/0xb0
[  221.438122] sp : ffff800012fdb820
[  221.441433] x29: ffff800012fdb820 x28: 0000000000000000
[  221.446743] x27: 0000000000000008 x26: ffff800011621f60
[  221.452053] x25: ffff0000c4b7f000 x24: ffff80001128d138
[  221.457364] x23: 0000000000000038 x22: ffff0000c18fea00
[  221.462674] x21: ffff800011d0ba70 x20: ffff0000c1873a00
[  221.467984] x19: ffff0000c1873a00 x18: 0000000000000030
[  221.473294] x17: 0000000000000000 x16: 0000000000000000
[  221.478604] x15: ffff0000c48d12b8 x14: ffffffffffffffff
[  221.483913] x13: ffff800011b51780 x12: 000000000000095a
[  221.489223] x11: 000000000000031e x10: ffff800011ba9780
[  221.494534] x9 : 00000000fffff000 x8 : ffff800011b51780
[  221.499844] x7 : ffff800011ba9780 x6 : 0000000000000000
[  221.505154] x5 : ffff00017f3ee900 x4 : 0000000000000000
[  221.510464] x3 : 0000000000000027 x2 : 0000000000000023
[  221.515774] x1 : f7f28654584c0c00 x0 : 0000000000000000
[  221.521085] Call trace:
[  221.523529]  clk_core_disable+0xa4/0xb0
[  221.527363]  clk_disable+0x34/0x50
[  221.530764]  lcdifv3_set_mode+0x40/0x2f0
[  221.534685]  lcdifv3_crtc_atomic_enable+0x88/0xcc
[  221.539387]  drm_atomic_helper_commit_modeset_enables+0x200/0x250
[  221.545478]  lcdifv3_drm_atomic_commit_tail+0x30/0x70
[  221.550526]  commit_tail+0xa0/0x180
[  221.554012]  drm_atomic_helper_commit+0x160/0x390
[  221.558714]  drm_atomic_commit+0x4c/0x60
[  221.562633]  drm_atomic_helper_commit_duplicated_state+0xf0/0x10c
[  221.568723]  drm_atomic_helper_resume+0x94/0x170
[  221.573338]  drm_mode_config_helper_resume+0x24/0x90
[  221.578299]  imx_drm_resume+0x14/0x20
[  221.581959]  platform_pm_resume+0x30/0x70
[  221.585968]  dpm_run_callback.constprop.0+0x3c/0xe4
[  221.590842]  device_resume+0x88/0x180
[  221.594501]  dpm_resume+0xe8/0x220
[  221.597900]  dpm_resume_end+0x18/0x30
[  221.601562]  suspend_devices_and_enter+0x1a4/0x5a0
[  221.606349]  pm_suspend+0x2e0/0x34c
[  221.609835]  state_store+0x8c/0x110
[  221.613323]  kobj_attr_store+0x1c/0x30
[  221.617070]  sysfs_kf_write+0x48/0x60
[  221.620730]  kernfs_fop_write_iter+0x118/0x1ac
[  221.625171]  new_sync_write+0xe8/0x180
[  221.628917]  vfs_write+0x244/0x2a4
[  221.632316]  ksys_write+0x6c/0x100
[  221.635714]  __arm64_sys_write+0x20/0x30
[  221.639636]  el0_svc_common.constprop.0+0x78/0x1a0
[  221.644423]  do_el0_svc+0x24/0x90
[  221.647737]  el0_svc+0x14/0x20
[  221.650789]  el0_sync_handler+0x1a4/0x1b0
[  221.654796]  el0_sync+0x180/0x1c0
[  221.658107] ---[ end trace c48b0b0e987f7565 ]---
[  221.662752] ------------[ cut here ]------------

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

Not all platform currently supports octal DTR mode. This causes flash
probe failure and therefore, provide an option of quirk
NXP_FSPI_QUIRK_DISABLE_DTR for platforms not supporting DTR.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>