[i.MX8] Add PWMs definition in dtsi file

This add-on regards the eight PWMs prensent into the LSIO part of the processor. This is due to the fact that in this version of kernel NXP has not included the nodes about these PWMs.
As reference the past kernel 4.19 (SECO internal) has been used.

Now it is possible to enable and use a pwm# node into dts of out boards.

arch/arm64/boot/dts/seco/include/imx8-ss-lsio.dtsi

@@ -316,4 +316,108 @@ lsio_subsys: bus@5d000000 {
 				     "pwm7_lpcg_ipg_mstr_clk";
 		power-domains = <&pd IMX_SC_R_PWM_7>;
 	};
+
+	pwm0: pwm@5d000000 {
+		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+		reg = <0x5d000000 0x10000>;
+		clocks = <&pwm0_lpcg 0>,
+		 	 <&pwm0_lpcg 1>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd IMX_SC_R_PWM_0>;
+		status = "disabled";
+	};
+
+	pwm1: pwm@5d010000 {
+		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+		reg = <0x5d010000 0x10000>;
+		clocks = <&pwm1_lpcg 0>,
+		 	 <&pwm1_lpcg 1>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd IMX_SC_R_PWM_1>;
+		status = "disabled";
+	};
+
+	pwm2: pwm@5d020000 {
+		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+		reg = <0x5d020000 0x10000>;
+		clocks = <&pwm2_lpcg 0>,
+		 	 <&pwm2_lpcg 1>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd IMX_SC_R_PWM_2>;
+		status = "disabled";
+	};
+
+	pwm3: pwm@5d030000 {
+		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+		reg = <0x5d030000 0x10000>;
+		clocks = <&pwm3_lpcg 0>,
+		 	 <&pwm3_lpcg 1>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd IMX_SC_R_PWM_3>;
+		status = "disabled";
+	};
+
+	pwm4: pwm@5d040000 {
+		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+		reg = <0x5d040000 0x10000>;
+		clocks = <&pwm4_lpcg 0>,
+		 	 <&pwm4_lpcg 1>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd IMX_SC_R_PWM_4>;
+		status = "disabled";
+	};
+
+	pwm5: pwm@5d050000 {
+		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+		reg = <0x5d050000 0x10000>;
+		clocks = <&pwm5_lpcg 0>,
+		 	 <&pwm5_lpcg 1>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd IMX_SC_R_PWM_5>;
+		status = "disabled";
+	};
+
+	pwm6: pwm@5d060000 {
+		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+		reg = <0x5d060000 0x10000>;
+		clocks = <&pwm6_lpcg 0>,
+		 	 <&pwm6_lpcg 1>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd IMX_SC_R_PWM_6>;
+		status = "disabled";
+	};
+
+	pwm7: pwm@5d070000 {
+		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x5d070000 0  0x10000>;
+		clocks = <&pwm7_lpcg 0>,
+			 <&pwm7_lpcg 1>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd IMX_SC_R_PWM_7>;
+		status = "disabled";
+	};
 };