arm64: dts: tanaro: Reduce pixelcklock frequency for scx1001255ggu06

Due to an unknown graphics pipeline issue we cannot use the correct
display settings for the SCX1001255GGU06 display. It seems that the
clocking and synchronization of the whole graphics pipeline consisting
of the LCDIF, the MIPI DSI, the MIPI PHY and the MIPI to LVDS
transceiver cannot be applied by simply changing the clock-frequency of
the attached panel.

Though trail and error we were not able to modify the pipeline clocking
in such a way that it works with the correct frequency.

Thus use the frequency from the fg0700w0dsswagl1 instead.

The display has a reduced frame rate, but otherwise works as expected.

arch/arm64/boot/dts/seconorth/scx1001255ggu06.dtsi

@@ -58,7 +58,13 @@ panel_lvds: panel {
 
 		/* Enable pin is shared with the sn65dsi83 */
 		panel-timing {
-			clock-frequency = <71107200>;
+			/* The following frequency 71.107200 MHz is valid 
+			 * for 60Hz fps. But somehow this does not work
+			 * clock-frequency = <71107200>;
+			 * Use the lower working clock, and reduce the fps to
+			 * ~43.
+			 */
+			clock-frequency = <51206400>;
 			hactive = <1280>;
 			vactive = <800>;
 			hfront-porch = <70>;