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arm64: dts: tanaro: Reduce pixelcklock frequency for scx1001255ggu06

Clemens Terasa requested to merge tanaro_add_scx1001255ggu06 into linux-5.15.32-seco

Due to an unknown graphics pipeline issue we cannot use the correct display settings for the SCX1001255GGU06 display. It seems that the clocking and synchronization of the whole graphics pipeline consisting of the LCDIF, the MIPI DSI, the MIPI PHY and the MIPI to LVDS transceiver cannot be applied by simply changing the clock-frequency of the attached panel.

Though trail and error we were not able to modify the pipeline clocking in such a way that it works with the correct frequency.

Thus use the frequency from the fg0700w0dsswagl1 instead.

The display has a reduced frame rate, but otherwise works as expected.

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