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Commit d050aa7e authored by Tobias Kahlki's avatar Tobias Kahlki
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arm64:dts: Clean-up fg0700w0dsswagl1 DT

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2 merge requests!455CI: Update gitlab-ci,!445Clean-up of devicetrees
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    arch/arm64/boot/dts/seconorth/fg0700w0dsswagl1.dtsi
    + 19
    − 19
    View file @ d050aa7e
    /* /*
    * Copyright 2020 Keith & Koep GmbH * Copyright 2020 Keith & Koep GmbH
    * * Copyright 2021-2024 SECO Northern Europe GmbH
    */ */
    /* /*
    ...@@ -13,24 +13,24 @@ TOUCH_RESET Defined in xxx_pinfunc.h. (SODIMM-pin: 75) ...@@ -13,24 +13,24 @@ TOUCH_RESET Defined in xxx_pinfunc.h. (SODIMM-pin: 75)
    */ */
    &cap_touch { &cap_touch {
    reg = <0x2a>; reg = <0x2a>;
    compatible = "eeti,exc3000_ts"; // out of tree driver compatible = "eeti,exc3000_ts"; // out of tree driver
    reset-low-active = <0>; reset-low-active = <0>;
    irq-low-active = <0>; irq-low-active = <0>;
    status = "okay"; status = "okay";
    }; };
    &mipi2lvds_bridge { &mipi2lvds_bridge {
    status = "okay"; status = "okay";
    }; };
    &panel_lvds{ &panel_lvds {
    status = "okay"; status = "okay";
    compatible = "panel-lvds"; compatible = "panel-lvds";
    data-mapping = "vesa-24"; data-mapping = "vesa-24";
    width-mm = <154>; width-mm = <154>;
    height-mm = <86>; height-mm = <86>;
    backlight = <&backlight1>; backlight = <&backlight1>;
    /* Enable pin is shared with the mipi to lvds bridge */ /* Enable pin is shared with the mipi to lvds bridge */
    ...@@ -44,7 +44,7 @@ panel-timing { ...@@ -44,7 +44,7 @@ panel-timing {
    vfront-porch = <17>; vfront-porch = <17>;
    vsync-len = <1>; vsync-len = <1>;
    vback-porch = <17>; vback-porch = <17>;
    }; };
    port { port {
    panel1_in: endpoint { panel1_in: endpoint {
    ...@@ -78,13 +78,13 @@ &dcss { ...@@ -78,13 +78,13 @@ &dcss {
    <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_AXI>,
    <&clk IMX8MQ_CLK_DISP_RTRM>; <&clk IMX8MQ_CLK_DISP_RTRM>;
    assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
    <&clk IMX8MQ_VIDEO_PLL1>, <&clk IMX8MQ_VIDEO_PLL1>,
    <&clk IMX8MQ_CLK_27M>, <&clk IMX8MQ_CLK_27M>,
    <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
    <&clk IMX8MQ_SYS1_PLL_800M>; <&clk IMX8MQ_SYS1_PLL_800M>;
    assigned-clock-rates = <600000000>, <0>, <0>, assigned-clock-rates = <600000000>, <0>, <0>,
    <800000000>, <800000000>,
    <400000000>; <400000000>;
    port@0 { port@0 {
    dcss_out: endpoint { dcss_out: endpoint {
    ......
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