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Commit b320dc65 authored by Jonas Höppner's avatar Jonas Höppner
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seco-mx8mm:tanaro:clk-pll14xx:video-pll1: Add additional setpoint for 700MHz

The pll only has a few preconfigured settings. This adds 700MHz
to achieve additional pixel clocks.

BCS 746-001034
parent 8759a147
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2 merge requests!455CI: Update gitlab-ci,!176seco-mx8mm:tanaro: Add support for FANNAL 10.1" and fix pixel clock for DataImage 10.1" display.
...@@ -57,6 +57,7 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { ...@@ -57,6 +57,7 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = { static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384), PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
PLL_1443X_RATE(700000000U, 350, 3, 2, 0),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0), PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
PLL_1443X_RATE(594000000U, 198, 2, 2, 0), PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
PLL_1443X_RATE(519750000U, 173, 2, 2, 16384), PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
......
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