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Commit 89848b5e authored by Jonas Höppner's avatar Jonas Höppner
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seco-mx8mm: Allow to specify the VIDIO_PLL1_RATE as define

This is a bit hacky but currently I don't know a better solution.

Though the doc say assigned-clock-parents may not be used to set clock rates
if there are multiple consumers this is used here widely.
( see Documentation/devicetree/bindings/clock/clock-bindings.txt line 164)
To allow to change this in devicetree using this file, this macro is
introduced, using the default value from before as default.

BCS 746-001034
parent afc2f905
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2 merge requests!455CI: Update gitlab-ci,!176seco-mx8mm:tanaro: Add support for FANNAL 10.1" and fix pixel clock for DataImage 10.1" display.
...@@ -13,6 +13,16 @@ ...@@ -13,6 +13,16 @@
#include "imx8mm-pinfunc.h" #include "imx8mm-pinfunc.h"
/* Though the doc say assigned-clock-parents may not be used to set clock rates
if there are multiple consumers this is used here widely.
( see Documentation/devicetree/bindings/clock/clock-bindings.txt line 164)
To allow to change this in devicetree using this file, this macro is
introduced, using the default value from before as default.
*/
#ifndef VIDEO_PLL1_RATE
#define VIDEO_PLL1_RATE 594000000
#endif
/ { / {
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
#address-cells = <2>; #address-cells = <2>;
...@@ -773,7 +783,7 @@ clk: clock-controller@30380000 { ...@@ -773,7 +783,7 @@ clk: clock-controller@30380000 {
<400000000>, <400000000>,
<400000000>, <400000000>,
<750000000>, <750000000>,
<594000000>, <VIDEO_PLL1_RATE>,
<393216000>, <393216000>,
<361267200>; <361267200>;
}; };
...@@ -1175,7 +1185,7 @@ lcdif: lcdif@32e00000 { ...@@ -1175,7 +1185,7 @@ lcdif: lcdif@32e00000 {
assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
<&clk IMX8MM_SYS_PLL2_1000M>, <&clk IMX8MM_SYS_PLL2_1000M>,
<&clk IMX8MM_SYS_PLL1_800M>; <&clk IMX8MM_SYS_PLL1_800M>;
assigned-clock-rate = <594000000>, <500000000>, <200000000>; assigned-clock-rate = <VIDEO_PLL1_RATE>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
lcdif-gpr = <&dispmix_gpr>; lcdif-gpr = <&dispmix_gpr>;
resets = <&lcdif_resets>; resets = <&lcdif_resets>;
...@@ -1203,7 +1213,7 @@ mipi_dsi: mipi_dsi@32e10000 { ...@@ -1203,7 +1213,7 @@ mipi_dsi: mipi_dsi@32e10000 {
<&clk IMX8MM_CLK_DSI_PHY_REF>; <&clk IMX8MM_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
<&clk IMX8MM_VIDEO_PLL1_OUT>; <&clk IMX8MM_VIDEO_PLL1_OUT>;
assigned-clock-rates = <266000000>, <594000000>; assigned-clock-rates = <266000000>, <VIDEO_PLL1_RATE>;
pref-rate = <11880>; pref-rate = <11880>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
dsi-gpr = <&dispmix_gpr>; dsi-gpr = <&dispmix_gpr>;
......
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