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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
*/
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/reset/imx8mp-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include "imx8mp-pinfunc.h"
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
i2c3 = &i2c4;
i2c4 = &i2c5;
i2c5 = &i2c6;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
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isi0 = &isi_0;
isi1 = &isi_1;
csi0 = &mipi_csi_0;
csi1 = &mipi_csi_1;
isp0 = &isp_0;
isp1 = &isp_1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
idle-states {
entry-method = "psci";
cpu_pd_wait: cpu-pd-wait {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010033>;
local-timer-stop;
entry-latency-us = <1000>;
exit-latency-us = <700>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
};
A53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
clock-latency = <61036>;
clocks = <&clk IMX8MP_CLK_ARM>;
operating-points-v2 = <&a53_opp_table>;
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
enable-method = "psci";
next-level-cache = <&A53_L2>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
clock-latency = <61036>;
clocks = <&clk IMX8MP_CLK_ARM>;
operating-points-v2 = <&a53_opp_table>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
clock-latency = <61036>;
clocks = <&clk IMX8MP_CLK_ARM>;
operating-points-v2 = <&a53_opp_table>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
clock-latency = <61036>;
clocks = <&clk IMX8MP_CLK_ARM>;
operating-points-v2 = <&a53_opp_table>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_L2: l2-cache0 {
compatible = "cache";
};
};
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&lcdif1_disp>,
<&lcdif2_disp>,
<&lcdif3_disp>;
};
a53_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <850000>;
opp-supported-hw = <0x8a0>, <0x7>;
clock-latency-ns = <150000>;
opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <950000>;
opp-supported-hw = <0xa0>, <0x7>;
clock-latency-ns = <150000>;
opp-suspend;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1000000>;
opp-supported-hw = <0x20>, <0x3>;
clock-latency-ns = <150000>;
opp-suspend;
};
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
resmem: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ocram: ocram@900000 {
no-map;
reg = <0 0x900000 0 0x70000>;
};
/*
* Memory reserved for optee usage. Please do not use.
* This will be automaticky added to dtb if OP-TEE is installed.
* optee@56000000 {
* reg = <0 0x56000000 0 0x2000000>;
* no-map;
* };
*/
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x3c000000>;
alloc-ranges = <0 0x40000000 0 0xC0000000>;
linux,cma-default;
};
dsp_reserved: dsp@92400000 {
reg = <0 0x92400000 0 0x1000000>;
no-map;
};
dsp_reserved_heap: dsp_reserved_heap {
reg = <0 0x93400000 0 0xef0000>;
no-map;
};
dsp_vdev0vring0: vdev0vring0@942f0000 {
reg = <0 0x942f0000 0 0x8000>;
no-map;
};
dsp_vdev0vring1: vdev0vring1@942f8000 {
reg = <0 0x942f8000 0 0x8000>;
no-map;
};
dsp_vdev0buffer: vdev0buffer@94300000 {
compatible = "shared-dma-pool";
reg = <0 0x94300000 0 0x100000>;
no-map;
};
/* used only by tuning tool, can be removed for normal case */
isp0_reserved: isp0@94400000 {
reg = <0 0x94400000 0 0x10000000>;
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};
};
osc_32k: clock-osc-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "osc_32k";
};
osc_24m: clock-osc-24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc_24m";
};
clk_ext1: clock-ext1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext1";
};
clk_ext2: clock-ext2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext2";
};
clk_ext3: clock-ext3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext3";
};
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <133000000>;
clock-output-names = "clk_ext4";
};
sai1_mclk: sai-mclk1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-output-names = "sai1_mclk";
};
sai2_mclk: sai-mclk2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-output-names = "sai2_mclk";
};
sai3_mclk: sai-mclk3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-output-names = "sai3_mclk";
};
sai5_mclk: sai-mclk5 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-output-names = "sai5_mclk";
};
sai6_mclk: sai-mclk6 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-output-names = "sai6_mclk";
};
sai7_mclk: sai-mclk7 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-output-names = "sai7_mclk";
};
busfreq { /* BUSFREQ */
compatible = "fsl,imx_busfreq";
clocks = <&clk IMX8MP_DRAM_PLL_OUT>, <&clk IMX8MP_CLK_DRAM_ALT>,
<&clk IMX8MP_CLK_DRAM_APB>, <&clk IMX8MP_CLK_DRAM_APB>,
<&clk IMX8MP_CLK_DRAM_CORE>, <&clk IMX8MP_CLK_DRAM_ALT_ROOT>,
<&clk IMX8MP_SYS_PLL1_40M>, <&clk IMX8MP_SYS_PLL1_100M>,
<&clk IMX8MP_SYS_PLL2_333M>, <&clk IMX8MP_CLK_NOC>,
<&clk IMX8MP_CLK_AHB>, <&clk IMX8MP_CLK_MAIN_AXI>,
<&clk IMX8MP_CLK_24M>, <&clk IMX8MP_SYS_PLL1_800M>,
clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div",
"dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m",
"sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m",
"sys_pll1_800m", "dram_pll_div";
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};
power-domains {
compatible = "simple-bus";
/* HSIO SS */
hsiomix_pd: hsiomix-pd {
compatible = "fsl,imx8m-pm-domain";
active-wakeup;
rpm-always-on;
#power-domain-cells = <0>;
domain-index = <0>;
domain-name = "hsiomix";
};
pcie_pd: pcie-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <1>;
domain-name = "pcie";
parent-domains = <&hsiomix_pd>;
};
usb_otg1_pd: usbotg1-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <2>;
domain-name = "usb_otg1";
parent-domains = <&hsiomix_pd>;
};
usb_otg2_pd: usbotg2-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <3>;
domain-name = "usb_otg2";
parent-domains = <&hsiomix_pd>;
};
/* MLMIX */
mlmix_pd: mlmix-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <4>;
domain-name = "mlmix";
clocks = <&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>,
<&clk IMX8MP_CLK_NPU_ROOT>;
};
audiomix_pd: audiomix-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <5>;
domain-name = "audiomix";
clocks = <&clk IMX8MP_CLK_AUDIO_AHB_ROOT>,
<&clk IMX8MP_CLK_AUDIO_AXI_ROOT>;
};
gpumix_pd: gpumix-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <6>;
domain-name = "gpumix";
clocks = <&clk IMX8MP_CLK_GPU_ROOT>, <&clk IMX8MP_CLK_GPU_AHB>,
<&clk IMX8MP_CLK_GPU_AXI>;
};
gpu2d_pd: gpu2d-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <7>;
domain-name = "gpu2d";
parent-domains = <&gpumix_pd>;
clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
};
gpu3d_pd: gpu3d-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <8>;
domain-name = "gpu3d";
parent-domains = <&gpumix_pd>;
clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
<&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
};
vpumix_pd: vpumix-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <9>;
domain-name = "vpumix";
clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
};
vpu_g1_pd: vpug1-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <10>;
domain-name = "vpu_g1";
parent-domains = <&vpumix_pd>;
clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
};
vpu_g2_pd: vpug2-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <11>;
domain-name = "vpu_g2";
parent-domains = <&vpumix_pd>;
clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
};
vpu_h1_pd: vpuh1-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <12>;
domain-name = "vpu_h1";
parent-domains = <&vpumix_pd>;
clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
};
mediamix_pd: mediamix-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <13>;
domain-name = "mediamix";
clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
};
ispdwp_pd: power-domain@14 {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <14>;
domain-name = "ispdwp";
parent-domains = <&mediamix_pd>;
};
mipi_phy1_pd: mipiphy1-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <15>;
domain-name = "mipi_phy1";
parent-domains = <&mediamix_pd>;
};
mipi_phy2_pd: mipiphy2-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <16>;
domain-name = "mipi_phy2";
parent-domains = <&mediamix_pd>;
};
hdmimix_pd: hdmimix-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <17>;
domain-name = "hdmimix";
clocks = <&clk IMX8MP_CLK_HDMI_ROOT>,
<&clk IMX8MP_CLK_HDMI_APB>,
<&clk IMX8MP_CLK_HDMI_REF_266M>;
};
hdmi_phy_pd: hdmiphy-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <18>;
domain-name = "hdmi_phy";
parent-domains = <&hdmimix_pd>;
};
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tmu 0>;
trips {
cpu_alert0: trip0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit0: trip1 {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
soc-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tmu 1>;
trips {
soc_alert0: trip0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
soc_crit0: trip1 {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&soc_alert0>;
cooling-device =
<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <8000000>;
arm,no-tick-in-suspend;
interrupt-parent = <&gic>;
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
nvmem-cells = <&imx8mp_uid>;
nvmem-cell-names = "soc_unique_id";
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caam_sm: caam-sm@100000 {
compatible = "fsl,imx6q-caam-sm";
reg = <0x100000 0x8000>;
};
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30000000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio1: gpio@30200000 {
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
reg = <0x30200000 0x10000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 5 30>;
};
gpio2: gpio@30210000 {
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
reg = <0x30210000 0x10000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 35 21>;
};
gpio3: gpio@30220000 {
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
reg = <0x30220000 0x10000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
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};
gpio4: gpio@30230000 {
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
reg = <0x30230000 0x10000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 82 32>;
};
gpio5: gpio@30240000 {
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
reg = <0x30240000 0x10000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 114 30>;
};
tmu: tmu@30260000 {
compatible = "fsl,imx8mp-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
#thermal-sensor-cells = <1>;
};
wdog1: watchdog@30280000 {
compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
status = "disabled";
};
wdog2: watchdog@30290000 {
compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
reg = <0x30290000 0x10000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
status = "disabled";
};
wdog3: watchdog@302a0000 {
compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
reg = <0x302a0000 0x10000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
status = "disabled";
};
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx8mp-iomuxc";
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
compatible = "fsl,imx8mp-iomuxc-gpr",
"fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
ocotp: efuse@30350000 {
compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon", "simple-mfd";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
/* For nvmem subnodes */
#address-cells = <1>;
#size-cells = <1>;
imx8mp_uid: unique-id@420 {
reg = <0x8 0x8>;
};
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
reg = <0x90 6>;
};
eth_mac2: mac-address@650 {
reg = <0x96 6>;
};
imx8mp_soc: imx8mp-soc {
compatible = "fsl,imx8mp-soc";
nvmem-cells = <&imx8mp_uid>;
nvmem-cell-names = "soc_unique_id";
};
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};
anatop: anatop@30360000 {
compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
"syscon";
reg = <0x30360000 0x10000>;
};
irq_sec_vio: caam_secvio {
compatible = "fsl,imx6q-caam-secvio";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
jtag-tamper = "disabled";
watchdog-tamper = "enabled";
internal-boot-tamper = "enabled";
external-pin-tamper = "disabled";
};
caam_snvs: caam-snvs@30370000 {
compatible = "fsl,imx6q-caam-snvs";
reg = <0x30370000 0x10000>;
clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
clock-names = "ipg";
};
snvs: snvs@30370000 {
compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
reg = <0x30370000 0x10000>;
snvs_rtc: snvs-rtc-lp {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap =<&snvs>;
offset = <0x34>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
clock-names = "snvs-rtc";
};
snvs_pwrkey: snvs-powerkey {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&snvs>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
clock-names = "snvs-pwrkey";
linux,keycode = <KEY_POWER>;
wakeup-source;
status = "disabled";
};
};
clk: clock-controller@30380000 {
compatible = "fsl,imx8mp-ccm";
reg = <0x30380000 0x10000>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
<&clk_ext3>, <&clk_ext4>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
<&clk IMX8MP_CLK_A53_CORE>,
<&clk IMX8MP_CLK_NOC>,
<&clk IMX8MP_CLK_NOC_IO>,
<&clk IMX8MP_CLK_GIC>,
<&clk IMX8MP_CLK_AUDIO_AHB>,
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
<&clk IMX8MP_AUDIO_PLL1>,
<&clk IMX8MP_AUDIO_PLL2>,
<&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_ARM_PLL_OUT>,
<&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL2_500M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <0>, <0>,
<1000000000>,
<800000000>,
<500000000>,
<400000000>,
<800000000>,
<393216000>,
<361267200>,
<1039500000>;
};
src: reset-controller@30390000 {
compatible = "fsl,imx8mp-src", "syscon";
reg = <0x30390000 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
};
aips2: bus@30400000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30400000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pwm1: pwm@30660000 {
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
reg = <0x30660000 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
<&clk IMX8MP_CLK_PWM1_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm2: pwm@30670000 {
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
reg = <0x30670000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
<&clk IMX8MP_CLK_PWM2_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm3: pwm@30680000 {
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
reg = <0x30680000 0x10000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
<&clk IMX8MP_CLK_PWM3_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm4: pwm@30690000 {
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
reg = <0x30690000 0x10000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
<&clk IMX8MP_CLK_PWM4_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
system_counter: timer@306a0000 {
compatible = "nxp,sysctr-timer";
reg = <0x306a0000 0x20000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc_24m>;
clock-names = "per";
};
};
aips3: bus@30800000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30800000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ecspi1: spi@30820000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30820000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
<&clk IMX8MP_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi2: spi@30830000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30830000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
<&clk IMX8MP_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi3: spi@30840000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30840000 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
<&clk IMX8MP_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@30860000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30860000 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
<&clk IMX8MP_CLK_UART1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart3: serial@30880000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30880000 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
<&clk IMX8MP_CLK_UART3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart2: serial@30890000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30890000 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
<&clk IMX8MP_CLK_UART2_ROOT>;
clock-names = "ipg", "per";
status = "disabled";
};
flexcan1: can@308c0000 {
compatible = "fsl,imx8mp-flexcan";
reg = <0x308c0000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
<&clk IMX8MP_CLK_CAN1_ROOT>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};
flexcan2: can@308d0000 {
compatible = "fsl,imx8mp-flexcan";
reg = <0x308d0000 0x10000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;