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  1. May 29, 2024
  2. May 28, 2024
  3. May 27, 2024
  4. May 24, 2024
  5. May 20, 2024
    • Gianfranco Mariotti's avatar
      [DRIVER] clk: imx: pll1443x: add PLL SSCG support · 23ee9c0f
      Gianfranco Mariotti authored
      In some situations, users might face EMI issues due to spikes around specific
      frequencies: enabling Spread Spectrum Clocking is indicated to reduce the
      electromagnetic peak around that specific frequency.
      
      From the i.MX8MP SoC Reference Manual document, Section 5.1.8 "CCM Analog
      Memory Map/Register Definition", the DRAM PLL, Audio PLL1, Audio PLL2 and
      Video PLL1 have available the spread spectrum function.
      
      The spread spectrum mode parameters of these PLLs can be calculated using
      the formulas below:
      * Modulation frequency: MF = Fin / p / mfr / (2^5) [Hz]
      * Modulation rate: MR = mfr * mrr / m / (2^6) × 100 [%: percentage of the PLL output frequency]
      * Where:
        * 0 <= mfr <= 255, 1 <= mrr <= 63, 0 <= mrr × mfr <= 512
        * Fin - PLL input clock frequency (typically, 24MHz = 24 * (10^6) Hz)
        * p = CCM_ANALOG_XXX_YYY_FDIV_CTL0[PLL_PRE_DIV] - reference frequency pre-divider value
        * m = CCM_ANALOG_XXX_YYY_FDIV_CTL0[PLL_MAIN_DIV] - PLL main divider value
        * mfr = CCM_ANALOG_XXX_YYY_SSCG_CTRL[PLL_MFREQ_CTL] - modulation frequency factor
        * mrr = CCM_ANALOG_XXX_YYY_SSCG_CTRL[PLL_MRAT_CTL] - modulation range factor
      
      fsl,imx8mm-anatop optional properties:
       - anatop-<$1>,sscg-enable
         - type: boolean
         - <$1>: PLL clk name
         - description: enable SSCG
       - anatop-<$1>,mfr
         - type: u32
         - <$1>: PLL clk name
         - description: modulation frequency control value
       - anatop-<$1>,mrr
         - type: u32
         - <$1>: PLL clk name
         - description: modulation rate control value
       - anatop-<$1>,sel-pf
         - type: u32
         - <$1>: PLL clk name
         - description: modulation method control value
      
      fsl,imx8mm-anatop dts example:
      &anatop {
        anatop-video_pll1,sscg-enable;
        anatop-video_pll1,mfr = <12>;
        anatop-video_pll1,mrr = <14>;
        anatop-video_pll1,sel-pf = <2>;
      };
      23ee9c0f
    • Gianfranco Mariotti's avatar
      [DRIVER] clk: imx: pll14xx: fix and use macros for FDIV_CTL regs · 6714a8fa
      Gianfranco Mariotti authored and Michele Cirinei's avatar Michele Cirinei committed
      Correct the definitions of "Divide and Fraction Data Control" registers,
      and use them in the appropriate code sections.
      6714a8fa
  6. May 16, 2024
  7. May 14, 2024
  8. May 03, 2024
  9. Apr 18, 2024
  10. Apr 12, 2024
    • Gianfranco Mariotti's avatar
      [D18] fine tune phy to pass HDMI CTS · a8c99791
      Gianfranco Mariotti authored and Michele Cirinei's avatar Michele Cirinei committed
      Fine tune hdmi phy to pass HDMI transmitter tests: fix failure on eye mask
      and voltage levels.
      a8c99791
    • Gianfranco Mariotti's avatar
      [i.MX8MP][DRIVER] phy: hdmi: add dts properties to set phy regs · a12ac37d
      Gianfranco Mariotti authored and Michele Cirinei's avatar Michele Cirinei committed
      dts properties:
       - phy-reg<$1>,clk<$2>
         - type: u8
         - <$1>: PHY_REG number
         - <$2>: specific clk-rate in Hz
         - description: set PHY_REG to u8 value for clk-rate
       - phy-reg<$1>
         - type: u8
         - <$1>: PHY_REG number
         - description: set PHY_REG to u8 value, has lower priority than
           clk-rate specific property
      a12ac37d
    • Joy Zou's avatar
      [PATCH] LF-5352: dmaengine: imx-sdma: fix the potential access registers without clock · e70e616a
      Joy Zou authored and Michele Cirinei's avatar Michele Cirinei committed
      
      The issue can be triggered with the sdma pm_runtime false.
      
      If the dma client try to use sdma in boot phase, it may cause
      system hang. The sdma driver really enable clk after sdma load
      firmware, the clk_disable_unused will disable the SDMA1_ROOT_CLK
      before the sdma driver enable clk. This issue will comes if access
      the sdma register when the SDMA1_ROOT_CLK is disable.
      
      This issue is very easy to reproduce with hdmi connected displayer
      on imx7d-sbd board which the i2c will use sdma early before sdma
      firmware loaded and clock enabled.
      
      The client i2c calls dmaengine_prep_slave_single->device_prep_slave_sg
      ->sdma_prep_slave_sg->sdma_config_write->sdma_config_channel to get
      descriptor in boot phase. Then, the function sdma_config_channel will
      access sdma registers. If clk is disable will cause system hang.
      
      This patch adds clk_enable and clk_disable to make sure the clk
      enable before access sdma hardware.
      
      Signed-off-by: default avatarJoy Zou <joy.zou@nxp.com>
      Reviewed-by: default avatarShengjiu Wang <shengjiu.wang@nxp.com>
      Reviewed-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
      Acked-by: default avatarJason Liu <jason.hui.liu@nxp.com>
      e70e616a
  11. Apr 11, 2024
  12. Apr 10, 2024
  13. Mar 27, 2024
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  15. Mar 12, 2024
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