[i.MX8MP][DRIVER] phy: hdmi: add dts properties to set phy regs

dts properties:
 - phy-reg<$1>,clk<$2>
   - type: u8
   - <$1>: PHY_REG number
   - <$2>: specific clk-rate in Hz
   - description: set PHY_REG to u8 value for clk-rate
 - phy-reg<$1>
   - type: u8
   - <$1>: PHY_REG number
   - description: set PHY_REG to u8 value, has lower priority than
     clk-rate specific property

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

@@ -929,6 +929,9 @@ static int samsung_hdmi_phy_clk_set_rate(struct clk_hw *hw,
 {
 	struct samsung_hdmi_phy *samsung = to_samsung_hdmi_phy(hw);
 	const struct phy_config *phy_cfg = samsung_phy_pll_cfg;
+	char property[30];
+	u32 readbuf;
+	u8 phy_off, phy_reg;
 	int i;
 
 	dev_dbg(samsung->dev, "%s\n", __func__);
@@ -946,6 +949,25 @@ static int samsung_hdmi_phy_clk_set_rate(struct clk_hw *hw,
 	for (i = 0; i < PHY_PLL_REGS_NUM; i++)
 		writeb(phy_cfg->regs[i], samsung->regs + i * 4);
 
+	/* DT: set HDMI PHY regs */
+	for (i = 1; i < PHY_PLL_REGS_NUM; i++) {
+		sprintf(property, "phy-reg%d,clk%d", i, phy_cfg->clk_rate); //clock-specific
+		if (!of_property_read_u32(samsung->dev->of_node, property, &readbuf)) {
+			phy_off = i * 4;
+			phy_reg = readbuf & 0xff;
+			dev_dbg(samsung->dev, "DT: set PHY_REG%d(0x%02x) to 0x%02x for clk-rate %dHz\n", i, phy_off, phy_reg, phy_cfg->clk_rate);
+			writeb(phy_reg, samsung->regs + phy_off);
+		} else {
+			sprintf(property, "phy-reg%d", i); //generic
+			if (!of_property_read_u32(samsung->dev->of_node, property, &readbuf)) {
+				phy_off = i * 4;
+				phy_reg = readbuf & 0xff;
+				dev_dbg(samsung->dev, "DT: set PHY_REG%d(0x%02x) to 0x%02x\n", i, phy_off, phy_reg);
+				writeb(phy_reg, samsung->regs + phy_off);
+			}
+		}
+	}
+
 	writeb(FIX_DA | MODE_SET_DONE , samsung->regs + PHY_REGS_84);
 
 	/* Wait for PHY PLL lock */