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- Sep 02, 2021
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Kuldeep Singh authored
Not all platform currently supports octal DTR mode. This causes flash probe failure and therefore, provide an option of quirk NXP_FSPI_QUIRK_DISABLE_DTR for platforms not supporting DTR. Signed-off-by:Kuldeep Singh <kuldeep.singh@nxp.com>
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Alice Guo authored
According to the FSB words list, the reserved 48 words are ahead of the bank 5. Reviewed-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
Alice Guo <alice.guo@nxp.com> Acked-by:
Jason Liu <jason.hui.liu@nxp.com>
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- Aug 31, 2021
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Haibo Chen authored
SDIO WiFi meet command/data crc error on some imx8ulp-evk RevB board, this is related to the known auto-tuning issue. Wifi interrupt conflict with auto-tuning logic, to workaround this, need to only check data0 for wifi device auto-tuning. So need to add property "fsl,sdio-interrupt-enabled" in dts file. Tested-by:
Sherry Sun <sherry.sun@nxp.com> Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
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- Aug 30, 2021
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Hemant Agrawal authored
1. fsl-ls1046a-rdb-usdpaa-shared-mac10.dts - MAC10 as shared port - all other ports to DPDK 2. fsl-ls1046a-rdb-shared-mac9-only.dts - MAC9 as shared port - all other ports to LINUX KERNEL Signed-off-by:Hemant Agrawal <hemant.agrawal@nxp.com>
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Hemant Agrawal authored
it was missing buffer pool initialization and dma-coherent property Signed-off-by: -
Nipun Gupta authored
This patch reducing the USDPAA reseved memory to 4K. In case USDPAA is to be used, 256MB needs to be reserved in the DTS file. Signed-off-by:Nipun Gupta <nipun.gupta@nxp.com>
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Li Jun authored
USB device mode u1 acception is enabled by default, this is good for power saving if there is no data transfer, if device side wants to start transfer while at u1, it can issue link change command to wakeup from u1 and transit to u0. Unfortunately on imx8mp/mq, we found a problem on this wakeup from u1, sometimes we need a very long time to transit to u0 after issue link change command, and the link change path shows the actual link change histry is u1->u2->u0, the right link change path should be u1->recovery->u0, this issue is still under check with Synopsys. Before the upstream patch commit b624b325 ("usb: dwc3: gadget: Fix START_TRANSFER link state check") merged, dwc3 driver did not check the actual link state for u1 and u2, a variable is used to record link state but never been set to u1 or u2, so we did not issue wakeup command before data transfer even the actual link state is at u1, the internal hardware should be able to handle this situation and transit to u0, so even a long time is required, we could not observe this because there is no error log, or function break on the whole. now with the fix commit pulled in, we start to check the real link state before every data transfer and issue a wakeup command if it is not at u0, if the wakeup can not complete in a polling of register read 20000 times, dwc3 driver will throw a warninng to user and continue data transfer anyway, so this underlying issue is exposed by this console log. This wakeup timeout issue also brings a side effect, as the 20000 times register polling is in a spinlock, which will impact other module iterrupt handling, considering this, we disable the u1 and u2 acception for device mode as a temporary solution before this issued is resovled. Reviewed-by:
Li Jun <jun.li@nxp.com> Acked-by:
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- Aug 27, 2021
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Shengjiu Wang authored
With multiple power domain case, don't need to use flag DL_FLAG_RPM_ACTIVE when device linking, otherwise the power is always enabled after probe. With DSP's case, the power may increase about 20% for whole system when DSP is enabled wrongly. Fixes: d2634e10 ("LF-4209-1: remoteproc: imx_dsp_rproc: add remoteproc driver for dsp") Signed-off-by:
Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by:
Peng Zhang <peng.zhang_8@nxp.com> Acked-by:
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Richard Zhu authored
PCIe r4.0 sec 6.6.1, Conventional Reset. The set of rules addresses requirements placed on the system: To allow components to perform internal initialization, system software must wait a specified minimum period following the end of a Conventional Reset before it is permitted to issue Configuration Request to the device immediately below that Port. - With a Downstream Port that does not support Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms before sending a Configuration Request to the device immediately below that Port. - With a Downstream Port that supports Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before sending a Configuration Request to the device immediately below that Port. Unfortunately, ther is a compatible link down issue when NEC Corporation uPD720200 USB 3.0 Host Controller (rev 04) is used on i.MX7D SDB board. When add the 100ms delay just at the end of the reset. To level up the compatibility and align with the SPEC, add the 100ms wait after the end of the PERST# toggle and link is up to fix the link down compatible issue when NEC uPD720200 is used on i.MX7D SDB board. And refer to PCIe r4.0 sec 6.6.1, A component must enter the LTSSM Detect state within 20 ms of the end of Fundamental Reset. To level up the compatibility of i.MX8MP PCIe to support one PLEXTOR NVME SSD device. Add one 20ms delay at the end of the PERST# toggle and before the start of the link training for i.MX8MP PCIe. Signed-off-by:
Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by:
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Richard Zhu authored
PCIe r4.0 sec 6.6.1, Conventional Reset. The set of rules addresses requirements placed on the system: To allow components to perform internal initialization, system software must wait a specified minimum period following the end of a Conventional Reset before it is permitted to issue Configuration Request to the device immediately below that Port. - With a Downstream Port that does not support Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms before sending a Configuration Request to the device immediately below that Port. - With a Downstream Port that supports Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before sending a Configuration Request to the device immediately below that Port. Unfortunately, ther is a compatible link down issue when NEC Corporation uPD720200 USB 3.0 Host Controller (rev 04) is used on i.MX7D SDB board. When add the 100ms delay just at the end of the reset. To level up the compatibility and align with the SPEC, add the 100ms wait after the end of the PERST# toggle and link is up. So, revert the commit 079f7245 ("LF-4081 PCI: imx: wait specified minimum period following the end of a reset") firstly. Signed-off-by:
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- Aug 24, 2021
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Liu Ying authored
Without this patch, the driver sets the DSI mode to 0x08 for RM67199, which means 'command RAM mode' as the panel data sheet indicates. In that mode, something like screen tearing effect can be seen when doing page flip test by using modetest. This patch changes the DSI mode to 0x0B for RM67199, which means 'video RAM capture mode' and aligns to the setting of RM67191. Fixes: ac708b5b ("MLK-24805-1: drm/panel: rm67191: Add support for rm67199") Cc: Sandor Yu <Sandor.yu@nxp.com> Cc: Robert Chiras <robert.chiras@nxp.com> Reviewed-by:
Sandor Yu <Sandor.yu@nxp.com> Signed-off-by:
Liu Ying <victor.liu@nxp.com> Acked-by:
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- Aug 23, 2021
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Liu Ying authored
When running the below system suspend/resume test case on i.MX8ulp EVK platform with the RM68200 MIPI DSI panel enabled, DCNANO display controller power usage count and pixel clock enable count would be unbalanced when the DRM connector's DPMS property is changed from off to on after system resumes, if the DPMS property is off before system suspends. The root cause is that the crtc_helper_funcs->mode_set_nofb() is called twice during the procedure without crtc disablement, one at system resume stage and one for DPMS on operation. That means the pm_runtime_get_sync() would be called twice at that function and pixel clock would be enabled twice as well. This patch introduces a flag to indicate if the modeset is done or not to avoid the doulbe modeset so that the reference counts are balanced. while true; do modetest -M imx-dcnano -w 34:DPMS:3; done & while true; do /unit_tests/SRTC/rtcwakeup.out -s 2 -m mem; done Fixes: ce68244e ("MLK-25531-2 drm/imx: Add dcnano drm support") Cc: Sandor Yu <Sandor.yu@nxp.com> Reviewed-by:
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Liu Ying authored
When running the below system suspend/resume test case on i.MX8ulp EVK platform with RM68200 MIPI DSI panel enabled, panel register access would fail when the DRM connector's DPMS property is changed from off to on after system resumes, if the DPMS property is off before system suspends. The root cause is that the bridge_funcs->mode_set() is called twice during the procedure without bridge disablement, one at system resume stage and one for DPMS on operation. That means the MIPI DPHY is not powered down during the procedure and initialized/powered on twice. As the PHY core driver takes reference count for the power on operation, the second power on operation doesn't take effect, hence the DPHY stays at the initialization status. This patch introduces a flag to indicate if the modeset is done or not to avoid the doulbe modeset so that the DPHY will be active when the panel registers are accessed. while true; do modetest -M imx-dcnano -w 34:DPMS:3; done & while true; do /unit_tests/SRTC/rtcwakeup.out -s 2 -m mem; done Fixes: 120ffd6b ("MLK-25574-4 drm/bridge: nwl-dsi: Get MIPI DSI controller and PHY ready in ->mode_set()") Cc: Sandor Yu <Sandor.yu@nxp.com> Reported-by:
Zhang Bo <bo.zhang@nxp.com> Reviewed-by:
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- Aug 20, 2021
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Shengjiu Wang authored
Fix copyright format：Copyright <year> NXP Signed-off-by:
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Shengjiu Wang authored
Fix copyright format：Copyright <year> NXP Signed-off-by:
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Rohit Raj authored
Fix crash observed in VSP while trying to get link status when link is down from kernel. Signed-off-by:
Rohit Raj <rohit.raj@nxp.com> DPDK-3239
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- Aug 18, 2021
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Diana Craciun authored
Currently when the device is reset, the entire DPRC container was reset which is very inefficient because the devices within a container will be reset multiple times. Added support for individually resetting a device. Signed-off-by:Diana Craciun <diana.craciun@oss.nxp.com>
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Diana Craciun authored
The open/reset/close commands format is similar for all objects. Currently there are multiple implementation for these commands scattered thorugh various drivers. The code is cavsi-identical. Create a generic implementation for the open/reset/close commands. One of the consumer will be the VFIO driver which needs to be able to reset a device. Signed-off-by:
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- Aug 13, 2021
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Robert-Ionut Alexa authored
The netdev should be unregistered before we are disconnecting from the MAC/PHY so that the dev_close callback is called and the PHY and the phylink workqueues are actually stopped before we are disconnecting and destroying the phylink instance. Fixes: 71947923 ("dpaa2-eth: add MAC/PHY support through phylink") Signed-off-by:
Robert-Ionut Alexa <robert-ionut.alexa@nxp.com>
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Jason Liu authored
After cdns DP API change, need use the correct dev for function DRM_DEV_ERROR otherwise, there will be module driver build issue. Signed-off-by:
Robby Cai <robby.cai@nxp.com>
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- Aug 12, 2021
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Shengjiu Wang authored
The regmap_config.max_register should match with regmap_config.reg_defaults definition, otherwise: [ 5.007222] ================================================================== [ 5.014592] BUG: KASAN: slab-out-of-bounds in regcache_flat_init+0xd0/0x120 [ 5.021635] Write of size 4 at addr ffff00000ab1d500 by task swapper/0/1 [ 5.028397] [ 5.029954] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.10.52-03729-gd820c2b9c5b0 #824 [ 5.037944] Hardware name: NXP i.MX8ULP EVK (DT) [ 5.042615] Call trace: [ 5.045142] dump_backtrace+0x0/0x2b4 [ 5.048884] show_stack+0x18/0x24 [ 5.052275] dump_stack+0xfc/0x168 [ 5.055757] print_address_description.constprop.0+0x6c/0x488 [ 5.061594] kasan_report+0x118/0x210 [ 5.065329] __asan_store4+0x98/0xd4 [ 5.068985] regcache_flat_init+0xd0/0x120 [ 5.073158] regcache_init+0x33c/0x72c [ 5.076982] __regmap_init+0xdf8/0x1730 [ 5.080896] __devm_regmap_init+0x70/0xc4 [ 5.084980] __devm_regmap_init_mmio_clk+0xd8/0x120 [ 5.089956] fsl_sai_probe+0x1c0/0xaf0 [ 5.093784] platform_drv_probe+0x70/0xd0 [ 5.097863] really_probe+0x148/0x704 [ 5.101595] driver_probe_device+0x78/0xec [ 5.105762] device_driver_attach+0x118/0x120 [ 5.110197] __driver_attach+0xb0/0x190 [ 5.114099] bus_for_each_dev+0xe8/0x160 [ 5.118092] driver_attach+0x34/0x44 [ 5.121736] bus_add_driver+0x1b8/0x2c0 [ 5.125641] driver_register+0xe0/0x210 [ 5.129552] __platform_driver_register+0x80/0x90 [ 5.134341] fsl_sai_driver_init+0x1c/0x28 [ 5.138512] do_one_initcall+0xa8/0x260 [ 5.142429] kernel_init_freeable+0x2cc/0x350 [ 5.146859] kernel_init+0x14/0x12c [ 5.150420] ret_from_fork+0x10/0x38 Fixes: 722eaf74 ("MLK-25556-7: ASoC: fsl_sai: add max_register in soc data") Signed-off-by:
Daniel Baluta <daniel.baluta@nxp.com> Reported-by:
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Guoniu.zhou authored
This reverts commit 1294e216. Signed-off-by:
Guoniu.zhou <guoniu.zhou@nxp.com> Reviewed-by:
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Guoniu.zhou authored
This reverts commit a70a560f. Signed-off-by:
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Guoniu.zhou authored
This reverts commit 5da3df26. Signed-off-by:
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Guoniu.zhou authored
This reverts commit 48acce75. Signed-off-by:
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Robby Cai authored
imx6ulz has no csi. delete csi and camera nodes to avoid confusion. Signed-off-by:
Alice Yuan <alice.yuan@nxp.com>
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Robby Cai authored
imx6ulz has no pxp, so remove pxp related nodes to avoid confusion. Signed-off-by:
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Daniel Baluta authored
Consecutive runs of cplay now fails because after first cplay the Firmware components states is not reset. We need to send SOF_IPC_STREAM_PCM_FREE command when a stream is closed in order to cleanup components states in Firmware. This will cause a pipeline reset and it will put the pipeline + components in a known state. Reviewed-by:
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- Aug 11, 2021
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Alice Yuan authored
fix kernel null point panic when basler camera output for m2m input pipeline created test cmd: gst-launch-1.0 v4l2src device=/dev/video3 ! video/x-raw,format=YUY2 ! v4l2convert ! video/x-raw, format=RGB ! videoconvert ! fakesink [ 80.780665] enter isp_s_comp [ 80.783562] enter isp_s_comp [ 80.806629] enter wdr3_hw_init [ 80.809714] wdr3 res: 3840 2160 CamEngineEnableCproc: set val 1 [ 80.813793] enter isp_mi_start 1 1 1.10 -15 1.00 0.00 [ 81.133511] isi-m2m 32e00000.isi:m2m_device: m2m_vb2_queue_setup [ 81.139585] isi-m2m 32e00000.isi:m2m_device: m2m_vb2_queue_setup, buf_n=2, planes[0]->size=16588800 [ 81.308157] isi-m2m 32e00000.isi:m2m_device: mxc_isi_m2m_job_ready [ 81.314419] isi-m2m 32e00000.isi:m2m_device: mxc_isi_m2m_device_run enter [ 81.321290] BUG: scheduling while atomic: v4l2src0:src/639/0x00000002 [ 81.327729] Modules linked in: vvcam_dwe(O) vvcam_video(O) vvcam_isp(O) imx8_media_dev(C) basler_camera_driver_vvcam(O) [ 81.338523] CPU: 0 PID: 639 Comm: v4l2src0:src Tainted: G C O 5.10.52-05403-g1994e5c9c0a1-dirty #1 [ 81.348605] Hardware name: NXP i.MX8MPlus EVK board (DT) [ 81.353912] Call trace: [ 81.356363] dump_backtrace+0x0/0x1a0 [ 81.360023] show_stack+0x18/0x70 [ 81.363339] dump_stack+0xd0/0x12c [ 81.366738] __schedule_bug+0x60/0x80 [ 81.370399] __schedule+0x67c/0x6d0 [ 81.373885] schedule+0x70/0x104 [ 81.377111] schedule_timeout+0x84/0xfc [ 81.380945] msleep+0x2c/0x40 [ 81.383912] mxc_isi_channel_enable+0x74/0xc0 [ 81.388266] mxc_isi_m2m_device_run+0x80/0xc0 [ 81.392620] v4l2_m2m_try_run+0x84/0x134 [ 81.396541] v4l2_m2m_ioctl_streamon+0x68/0x80 [ 81.400982] mxc_isi_m2m_streamon+0x70/0xbc [ 81.405163] v4l_streamon+0x28/0x34 [ 81.408650] __video_do_ioctl+0x180/0x3e4 [ 81.412658] video_usercopy+0x1a0/0x450 [ 81.416491] video_ioctl2+0x18/0x24 [ 81.419978] v4l2_ioctl+0x44/0x64 [ 81.423292] __arm64_sys_ioctl+0xa8/0xf0 [ 81.427213] el0_svc_common.constprop.0+0x78/0x1a0 [ 81.432001] do_el0_svc+0x24/0x90 [ 81.435314] el0_svc+0x14/0x20 [ 81.438366] el0_sync_handler+0x1a4/0x1b0 [ 81.442373] el0_sync+0x180/0x1c0 [ 81.445745] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000a60 [ 81.454530] Mem abort info: [ 81.457320] ESR = 0x96000004 [ 81.460371] EC = 0x25: DABT (current EL), IL = 32 bits [ 81.465679] SET = 0, FnV = 0 [ 81.468729] EA = 0, S1PTW = 0 [ 81.471866] Data abort info: [ 81.474743] ISV = 0, ISS = 0x00000004 [ 81.478575] CM = 0, WnR = 0 [ 81.481539] user pgtable: 4k pages, 48-bit VAs, pgdp=00000001064d0000 [ 81.487975] [0000000000000a60] pgd=0000000000000000, p4d=0000000000000000 [ 81.494764] Internal error: Oops: 96000004 [#1] PREEMPT SMP [ 81.500333] Modules linked in: vvcam_dwe(O) vvcam_video(O) vvcam_isp(O) imx8_media_dev(C) basler_camera_driver_vvcam(O) [ 81.511124] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G WC O 5.10.52-05403-g1994e5c9c0a1-dirty #1 [ 81.520773] Hardware name: NXP i.MX8MPlus EVK board (DT) [ 81.526082] pstate: 40000085 (nZcv daIf -PAN -UAO -TCO BTYPE=--) [ 81.532092] pc : mxc_isi_cap_frame_write_done+0x2c/0x1fc [ 81.537401] lr : mxc_isi_irq_handler+0x84/0x90 [ 81.541840] sp : ffff800011d0bbf0 [ 81.545150] x29: ffff800011d0bbf0 x28: ffff800011b02340 [ 81.550461] x27: 0000000000000280 x26: ffff8000115d2c90 [ 81.555771] x25: ffff800011c4856a x24: 00000000000016c8 [ 81.561082] x23: 0000000000000039 x22: ffff0000c18a1530 [ 81.566393] x21: 0000000000001600 x20: 0000000060020100 [ 81.571703] x19: 0000000000000000 x18: 0000000000000030 [ 81.577013] x17: 0000000000000000 x16: 0000000000000000 [ 81.582324] x15: 0000000fcc57dcca x14: 00000000000000ed [ 81.587634] x13: 0000000000000000 x12: 0000000000000040 [ 81.592946] x11: ffff0000c20a5ff0 x10: ffff0000c20a5ff2 [ 81.598257] x9 : ffff800011b81788 x8 : ffff0000c2000270 [ 81.603567] x7 : 0000000000000000 x6 : ffff0000c2000430 [ 81.608878] x5 : ffff0000c2000248 x4 : 00000000000016c8 [ 81.614188] x3 : 0000000000001600 x2 : 0000000000000001 [ 81.619499] x1 : 0000000060020100 x0 : ffff0000c18a1480 [ 81.624809] Call trace: [ 81.627255] mxc_isi_cap_frame_write_done+0x2c/0x1fc [ 81.632217] mxc_isi_irq_handler+0x84/0x90 [ 81.636312] __handle_irq_event_percpu+0x54/0x170 [ 81.641013] handle_irq_event+0x68/0x150 [ 81.644934] handle_fasteoi_irq+0xa4/0x1f4 [ 81.649027] __handle_domain_irq+0x7c/0xe0 [ 81.653122] gic_handle_irq+0xc0/0x140 [ 81.656869] el1_irq+0xcc/0x180 [ 81.660007] efi_header_end+0xa4/0x290 [ 81.663754] irq_exit+0xdc/0xfc [ 81.666893] __handle_domain_irq+0x80/0xe0 [ 81.670986] gic_handle_irq+0xc0/0x140 [ 81.674732] el1_irq+0xcc/0x180 [ 81.677875] _raw_spin_unlock_irq+0x14/0x50 [ 81.682056] __schedule+0x260/0x6d0 [ 81.685543] schedule_idle+0x28/0x50 [ 81.689117] do_idle+0x198/0x2a0 [ 81.692343] cpu_startup_entry+0x24/0x70 [ 81.696263] rest_init+0xd8/0xe8 [ 81.699491] arch_call_rest_init+0x10/0x1c [ 81.703584] start_kernel+0x4ac/0x4e4 [ 81.707247] Code: a90363f7 f9400013 8b030275 8b040278 (f9453277) [ 81.713344] ---[ end trace 1a1c3af55549f42e ]--- [ 81.717959] Kernel panic - not syncing: Oops: Fatal exception in interrupt [ 81.724830] SMP: stopping secondary CPUs [ 81.729069] Kernel Offset: disabled [ 81.732555] CPU features: 0x0240002,2000200c [ 81.736820] Memory Limit: none root cause: when user is multi-processing "imx-isi-m2m" node, the driver of "imx-isi-m2m" open and close should have concurrent protection. Signed-off-by:
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Jiyu Yang authored
Signed-off-by:Jiyu Yang <jiyu.yang@nxp.com>
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- Aug 10, 2021
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Adrian Alonso authored
Add device tree to enable meidum quality sound support for iMX7D SabreSD, MQS_L/MQS_R pins on J20. Signed-off-by:
Adrian Alonso <adrian.alonso@nxp.com> Reviewed-by:
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Robby Cai authored
previous one IMX8ULP_CLK_PLL4_PFD0_DIV1 is shared with DC Nano, which could be changed in some cases. use IMX8ULP_CLK_PLL4_PFD0_DIV2 for EPDC. Signed-off-by:
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Robby Cai authored
This is workaround for EPDC driver on MX8ULP as the driver doesn't handle well enough currently. Signed-off-by:
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Robby Cai authored
EPDC and PXP shares same power domain. Signed-off-by:
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Robby Cai authored
Fix unbalanced disables for regulators. this can be reproduced when run 'reboot'. ... [ 4793.240673] systemd-shutdown[1]: Rebooting. [ 4793.244917] kvm: exiting hardware virtualization [ 4793.249696] ------------[ cut here ]------------ [ 4793.254293] unbalanced disables for VCOM [ 4793.258276] WARNING: CPU: 0 PID: 1 at drivers/regulator/core.c:2759 _regulator_disable+0xd4/0x190 [ 4793.267035] Modules linked in: [ 4793.270067] CPU: 0 PID: 1 Comm: systemd-shutdow Not tainted 5.10.52-03704-gc6da78873546-dirty #83 [ 4793.278818] Hardware name: NXP i.MX8ULP EVK (DT) [ 4793.283381] pstate: 60000005 (nZCv daif -PAN -UAO -TCO BTYPE=--) [ 4793.289305] pc : _regulator_disable+0xd4/0x190 [ 4793.293690] lr : _regulator_disable+0xd4/0x190 [ 4793.298072] sp : ffff800011d3bbf0 [ 4793.301346] x29: ffff800011d3bbf0 x28: ffff000004080000 [ 4793.306599] x27: 0000000000000000 x26: ffff800011684f38 [ 4793.311849] x25: 0000000000000008 x24: ffff800011c8c030 [ 4793.317099] x23: ffff00000424c490 x22: ffff800011cebb88 [ 4793.322349] x21: ffff0000058d4800 x20: ffff0000058e6b00 [ 4793.327598] x19: ffff000004080000 x18: 0000000000000030 [ 4793.332851] x17: 0000000000000000 x16: 0000000000000000 [ 4793.338103] x15: ffff000004080478 x14: 00000000000003d1 [ 4793.343351] x13: 0000000000000000 x12: 0000000000000000 [ 4793.348602] x11: 0000000000000000 x10: 00000000000009d0 [ 4793.353853] x9 : ffff800011d3b920 x8 : ffff000004080a30 [ 4793.359101] x7 : ffff000057bd1a00 x6 : 00000000000003cd [ 4793.364351] x5 : 0000000000000004 x4 : 0000000000000000 [ 4793.369602] x3 : ffff000008a465d0 x2 : ffff800011b316f8 [ 4793.374851] x1 : 53f88fcddf009600 x0 : 0000000000000000 [ 4793.380098] Call trace: [ 4793.382516] _regulator_disable+0xd4/0x190 [ 4793.386555] regulator_disable+0x40/0x80 [ 4793.390431] mxc_epdc_fb_shutdown+0x100/0x130 [ 4793.394739] platform_drv_shutdown+0x24/0x3c [ 4793.398958] device_shutdown+0x158/0x330 [ 4793.402832] __do_sys_reboot+0x1f0/0x294 [ 4793.406709] __arm64_sys_reboot+0x28/0x3c [ 4793.410668] el0_svc_common.constprop.0+0x78/0x1a0 [ 4793.415401] do_el0_svc+0x24/0x90 [ 4793.418675] el0_svc+0x14/0x20 [ 4793.421695] el0_sync_handler+0x1a4/0x1b0 [ 4793.425654] el0_sync+0x180/0x1c0 [ 4793.428922] ---[ end trace d2acbee35af03638 ]--- ... Signed-off-by:
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Robby Cai authored
Access register HW_PXP_WFE_A_STG1_8X1_OUT1_0/1 causes Asynchronous SError Interrupt. Skip pxp_lut_cleanup_multiple() to skip above registers access to workaround it. reproduce step: run '/unit_tests/Display/mxc_epdc_v2_fb_test.out' ... *** Try again at 1,1 *** [ 153.808422] SError Interrupt on CPU1, code 0xbf000002 -- SError [ 153.808431] CPU: 1 PID: 124 Comm: pxp_dispatch Not tainted 5.10.52-02305-gd72ff8b018b0-dirty #7 [ 153.808435] Hardware name: NXP i.MX8ULP EVK (DT) [ 153.808441] pstate: 60000085 (nZCv daIf -PAN -UAO -TCO BTYPE=--) [ 153.808445] pc : pxp_wfe_a_process+0xec/0x28c [ 153.808449] lr : pxp_dispatch_thread+0x1758/0x2430 [ 153.808453] sp : ffff80001247bd40 [ 153.808457] x29: ffff80001247bd40 x28: ffff000008a8c080 [ 153.808471] x27: ffff0000054f8080 x26: ffff000008a8c000 [ 153.808480] x25: ffff800011cd2000 x24: ffff800011cd2028 [ 153.808490] x23: ffff0000054f80a4 x22: fffffffffffffffc [ 153.808499] x21: 0000000000000040 x20: ffff0000054f8080 [ 153.808509] x19: ffff0000054f9480 x18: 0000000000001b90 [ 153.808518] x17: 0000000000001b80 x16: 0000000000001c60 [ 153.808528] x15: 0000000000001c50 x14: 0000000000001c40 [ 153.808537] x13: 0000000000001c30 x12: 0000000000001c20 [ 153.808546] x11: 0000000000001c10 x10: 0000000000001400 [ 153.808556] x9 : 0000000000001bf0 x8 : 0000000000000000 [ 153.808565] x7 : 0000000000000400 x6 : 0000000000000000 [ 153.808574] x5 : ffff800012750ca0 x4 : 0000000000000000 [ 153.808584] x3 : 00000000000002f5 x2 : 00000000000002f6 [ 153.808593] x1 : ffff800012750000 x0 : 00000000000003ff [ 153.808604] Kernel panic - not syncing: Asynchronous SError Interrupt [ 153.808610] CPU: 1 PID: 124 Comm: pxp_dispatch Not tainted 5.10.52-02305-gd72ff8b018b0-dirty #7 [ 153.808614] Hardware name: NXP i.MX8ULP EVK (DT) [ 153.808618] Call trace: [ 153.808622] dump_backtrace+0x0/0x1a0 [ 153.808626] show_stack+0x18/0x70 [ 153.808630] dump_stack+0xd0/0x12c [ 153.808633] panic+0x16c/0x334 [ 153.808637] nmi_panic+0x8c/0x90 [ 153.808641] arm64_serror_panic+0x78/0x84 [ 153.808644] do_serror+0x64/0x6c [ 153.808648] el1_error+0x90/0x110 [ 153.808652] pxp_wfe_a_process+0xec/0x28c [ 153.808656] pxp_dispatch_thread+0x1758/0x2430 [ 153.808660] kthread+0x154/0x160 [ 153.808664] ret_from_fork+0x10/0x30 [ 153.808697] SMP: stopping secondary CPUs [ 153.808701] Kernel Offset: disabled [ 153.808705] CPU features: 0x0240002,20002008 [ 153.808709] Memory Limit: none Signed-off-by:
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Clark Wang authored
If enable interrupt in the svc_i3c_master_bus_init() but do not call enable ibi in the device driver, it will cause a kernel dump in the svc_i3c_master_handle_ibi() when a slave start occurs on the i3c bus, because the data->ibi_pool is not initialized. So only enable the interrupt in svc_i3c_master_enable_ibi() function. Signed-off-by:
Clark Wang <xiaoning.wang@nxp.com> Reviewed-by:
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Clark Wang authored
The label of GPIO is all "vf610-gpio" in rootfs before. Use its module name to fill the GPIO labels. So that we can distinguish them more conveniently in rootfs. Signed-off-by:
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Clark Wang authored
The label of GPIO is all "imx-rpmsg-gpio" in rootfs before. Add its module index into its GPIO labels. So that we can distinguish them more conveniently in rootfs. Signed-off-by:
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Sandor Yu authored
Correct copyright description with the format: Copyright <year range> NXP description. Signed-off-by:
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