Do not need to read quite large data through i2c bus, accroding to driver
logic, only need the first 8 byte data. So change this length to 9.

Add this change also can fix one error on imx8ulp-evk board, because the
touch is on rpmsg-i2c bus, rpmsg limitate the data size, can't be large
than 14 byte. If config a large data size, will trigger i2c error.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

Currently on imx8ulp-evk board, the interrupt pin we use is from M core
domain, need use gpio-rpmsg to handle the interrupt. If frequently free
or request this irq during suspend/resume, system will randomly hang.
As a workaround, just disable/enable instead.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

After we start to do core soft reset while switch to device
mode, the phy init will be done at every switch, but its counter
part de-init is missing, this cause the phy init and exit is not
balanced, then when we really need do phy init like system resume,
it will not be done by phy driver because the maintained counter
is not 0. Considering actually phy init is redundant while mode
switch, so move out the phy init to dwc3 core init where is the
only place required.

Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Tested-by: faqiang.zhu <faqiang.zhu@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

In SDIO mode, auto-tuning only support 1-bit mode as device sends
an async interrupt to uSDHC through DAT1 during interrupt period
which implies 4-bit auto tuning is not supported under SDIO mode.

Reviewed-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

The same patch "net: sched: add barrier to ensure correct
ordering for lockless qdisc" is duplicated with these
two commit ID (e7c3ae47
and 9486b3dd) in the process
of merge(commid ID: 8b0b3faf):

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>

The variable 'ext_temp' presenting the external temperature is expected to be
used when call with DEFAULT_TEMP_INDEX and overridden by new value if read out
successfully from the PMIC. For some reason sometimes the temperature value from
PMIC is not correct on MX8ULP (e.g., read out as '0'), disable it temporarily.
As a consequence, it causes the variable 'ext_temp' might be uninitialized
and then set a wrong temperature index to register.

This patch fixed this Uninitialized problem by setting to DEFAULT_TEMP.

Current logic is the driver will use DEFAULT_TEMP unless the user assigns
different value. To revisit PMIC temperature driver to restore previous logic.

Signed-off-by: Robby Cai <robby.cai@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

Fix below section mismatch build warning:

WARNING: modpost: vmlinux.o(.text+0x6b20b8): Section mismatch in reference
from the function imx8_soc_info() to the function .init.text:imx8mq_noc_init()
The function imx8_soc_info() references
the function __init imx8mq_noc_init().
This is often because imx8_soc_info lacks a __init
annotation or the annotation of imx8mq_noc_init is wrong.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

Fix below section mismatch build warning in imx8mm/mn/mq clock driver:

WARNING: modpost: vmlinux.o(.text+0x667618): Section mismatch in reference
from the function imx8mm_clocks_probe() to the function .init.text:imx_clk_init_on.isra.0()
The function imx8mm_clocks_probe() references
the function __init imx_clk_init_on.isra.0().
This is often because imx8mm_clocks_probe lacks a __init
annotation or the annotation of imx_clk_init_on.isra.0 is wrong.

WARNING: modpost: vmlinux.o(.text+0x66a034): Section mismatch in reference
from the function imx8mn_clocks_probe() to the function .init.text:imx_clk_init_on.isra.0()
The function imx8mn_clocks_probe() references
the function __init imx_clk_init_on.isra.0().
This is often because imx8mn_clocks_probe lacks a __init
annotation or the annotation of imx_clk_init_on.isra.0 is wrong.

WARNING: modpost: vmlinux.o(.text+0x6713f8): Section mismatch in reference
from the function imx8mq_clocks_probe() to the function .init.text:imx_clk_init_on.isra.0()
The function imx8mq_clocks_probe() references
the function __init imx_clk_init_on.isra.0().
This is often because imx8mq_clocks_probe lacks a __init
annotation or the annotation of imx_clk_init_on.isra.0 is wrong.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

For i.MX8MN DDR3L EVK board, it uses a 11x11 package that VDD_ARM & VDD_SOC
is combined together, the 'cpu-supply' should be buck1, so correct it.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

Enable configs for AF_ALG socket based interface to Kernel cryptography
CONFIG_CRYPTO_USER_API_HASH
CONFIG_CRYPTO_USER_API_SKCIPHER
CONFIG_CRYPTO_USER_API_AEAD

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Varun Sethi <v.sethi@nxp.com>
Reviewed-by: Silvano Di Ninno <silvano.dininno@nxp.com>

update base_bd_ptr for channel0 after bd0 descriptor allocated again.
Otherwise, sdma may hang if the stale/wrong bd0 data touched by channel0
as below:

[  221.334360] imx-sdma 30e10000.dma-controller: Timeout waiting for CH0 ready
[  221.341333] imx-sdma 30e10000.dma-controller: save context error!
[  221.347437] PM: dpm_run_callback(): sdma_suspend+0x0/0x160 returns -110
[  221.354054] PM: Device 30e10000.dma-controller failed to suspend late: error -110
[  221.361937] PM: late suspend of devices failed
[  221.370127] ------------[ cut here ]------------
[  221.374745] lcdif_pixel_clk already disabled
[  221.379050] WARNING: CPU: 0 PID: 4510 at drivers/clk/clk.c:952 clk_core_disable+0xa4/0xb0
[  221.387222] Modules linked in: snvs_ui(O) fsl_jr_uio caam_jr caamkeyblob_desc caamhash_desc caamalg_desc crypto_engine rng_core authenc libdes crct10dif_ce imx8_media_dev(C) flexcan can_dev caam secvio error fuse [last unloaded: snvs_ui]
[  221.408283] CPU: 0 PID: 4510 Comm: rtc_wakeup.sh Tainted: G         C O      5.10.52-lts-5.10.y+g5788c4507376 #1
[  221.418451] Hardware name: NXP i.MX8MPlus EVK board (DT)
[  221.423761] pstate: 40000085 (nZcv daIf -PAN -UAO -TCO BTYPE=--)
[  221.429764] pc : clk_core_disable+0xa4/0xb0
[  221.433943] lr : clk_core_disable+0xa4/0xb0
[  221.438122] sp : ffff800012fdb820
[  221.441433] x29: ffff800012fdb820 x28: 0000000000000000
[  221.446743] x27: 0000000000000008 x26: ffff800011621f60
[  221.452053] x25: ffff0000c4b7f000 x24: ffff80001128d138
[  221.457364] x23: 0000000000000038 x22: ffff0000c18fea00
[  221.462674] x21: ffff800011d0ba70 x20: ffff0000c1873a00
[  221.467984] x19: ffff0000c1873a00 x18: 0000000000000030
[  221.473294] x17: 0000000000000000 x16: 0000000000000000
[  221.478604] x15: ffff0000c48d12b8 x14: ffffffffffffffff
[  221.483913] x13: ffff800011b51780 x12: 000000000000095a
[  221.489223] x11: 000000000000031e x10: ffff800011ba9780
[  221.494534] x9 : 00000000fffff000 x8 : ffff800011b51780
[  221.499844] x7 : ffff800011ba9780 x6 : 0000000000000000
[  221.505154] x5 : ffff00017f3ee900 x4 : 0000000000000000
[  221.510464] x3 : 0000000000000027 x2 : 0000000000000023
[  221.515774] x1 : f7f28654584c0c00 x0 : 0000000000000000
[  221.521085] Call trace:
[  221.523529]  clk_core_disable+0xa4/0xb0
[  221.527363]  clk_disable+0x34/0x50
[  221.530764]  lcdifv3_set_mode+0x40/0x2f0
[  221.534685]  lcdifv3_crtc_atomic_enable+0x88/0xcc
[  221.539387]  drm_atomic_helper_commit_modeset_enables+0x200/0x250
[  221.545478]  lcdifv3_drm_atomic_commit_tail+0x30/0x70
[  221.550526]  commit_tail+0xa0/0x180
[  221.554012]  drm_atomic_helper_commit+0x160/0x390
[  221.558714]  drm_atomic_commit+0x4c/0x60
[  221.562633]  drm_atomic_helper_commit_duplicated_state+0xf0/0x10c
[  221.568723]  drm_atomic_helper_resume+0x94/0x170
[  221.573338]  drm_mode_config_helper_resume+0x24/0x90
[  221.578299]  imx_drm_resume+0x14/0x20
[  221.581959]  platform_pm_resume+0x30/0x70
[  221.585968]  dpm_run_callback.constprop.0+0x3c/0xe4
[  221.590842]  device_resume+0x88/0x180
[  221.594501]  dpm_resume+0xe8/0x220
[  221.597900]  dpm_resume_end+0x18/0x30
[  221.601562]  suspend_devices_and_enter+0x1a4/0x5a0
[  221.606349]  pm_suspend+0x2e0/0x34c
[  221.609835]  state_store+0x8c/0x110
[  221.613323]  kobj_attr_store+0x1c/0x30
[  221.617070]  sysfs_kf_write+0x48/0x60
[  221.620730]  kernfs_fop_write_iter+0x118/0x1ac
[  221.625171]  new_sync_write+0xe8/0x180
[  221.628917]  vfs_write+0x244/0x2a4
[  221.632316]  ksys_write+0x6c/0x100
[  221.635714]  __arm64_sys_write+0x20/0x30
[  221.639636]  el0_svc_common.constprop.0+0x78/0x1a0
[  221.644423]  do_el0_svc+0x24/0x90
[  221.647737]  el0_svc+0x14/0x20
[  221.650789]  el0_sync_handler+0x1a4/0x1b0
[  221.654796]  el0_sync+0x180/0x1c0
[  221.658107] ---[ end trace c48b0b0e987f7565 ]---
[  221.662752] ------------[ cut here ]------------

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

Not all platform currently supports octal DTR mode. This causes flash
probe failure and therefore, provide an option of quirk
NXP_FSPI_QUIRK_DISABLE_DTR for platforms not supporting DTR.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>

According to the FSB words list, the reserved 48 words are ahead of the
bank 5.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

SDIO WiFi meet command/data crc error on some imx8ulp-evk RevB board, this
is related to the known auto-tuning issue. Wifi interrupt conflict with
auto-tuning logic, to workaround this, need to only check data0 for wifi
device auto-tuning. So need to add property "fsl,sdio-interrupt-enabled"
in dts file.

Tested-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

1. fsl-ls1046a-rdb-usdpaa-shared-mac10.dts  - MAC10 as shared port - all
other ports to DPDK

2. fsl-ls1046a-rdb-shared-mac9-only.dts  - MAC9 as shared port - all
other ports to LINUX KERNEL

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>

it was missing buffer pool initialization and dma-coherent property

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>

This patch reducing the USDPAA reseved memory to 4K.
In case USDPAA is to be used, 256MB needs to be reserved in the DTS file.

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>

USB device mode u1 acception is enabled by default, this is
good for power saving if there is no data transfer, if device
side wants to start transfer while at u1, it can issue link
change command to wakeup from u1 and transit to u0.

Unfortunately on imx8mp/mq, we found a problem on this wakeup
from u1, sometimes we need a very long time to transit to u0
after issue link change command, and the link change path shows
the actual link change histry is u1->u2->u0, the right link
change path should be u1->recovery->u0, this issue is still
under check with Synopsys.

Before the upstream patch commit b624b325
("usb: dwc3: gadget: Fix START_TRANSFER link state check")
merged, dwc3 driver did not check the actual link state for
u1 and u2, a variable is used to record link state but never been
set to u1 or u2, so we did not issue wakeup command before
data transfer even the actual link state is at u1, the internal
hardware should be able to handle this situation and transit
to u0, so even a long time is required, we could not observe
this because there is no error log, or function break on the whole.
now with the fix commit pulled in, we start to check the real
link state before every data transfer and issue a wakeup command
if it is not at u0, if the wakeup can not complete in a polling
of register read 20000 times, dwc3 driver will throw a warninng
to user and continue data transfer anyway, so this underlying
issue is exposed by this console log.

This wakeup timeout issue also brings a side effect, as the
20000 times register polling is in a spinlock, which will impact
other module iterrupt handling, considering this, we disable the
u1 and u2 acception for device mode as a temporary solution before
this issued is resovled.

Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

With multiple power domain case, don't need to use flag
DL_FLAG_RPM_ACTIVE when device linking, otherwise the power
is always enabled after probe.

With DSP's case, the power may increase about 20% for whole system
when DSP is enabled wrongly.

Fixes: d2634e10 ("LF-4209-1: remoteproc: imx_dsp_rproc: add remoteproc driver for dsp")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Peng Zhang <peng.zhang_8@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

PCIe r4.0 sec 6.6.1, Conventional Reset.
The set of rules addresses requirements placed on the system:
To allow components to perform internal initialization, system
software must wait a specified minimum period following the
end of a Conventional Reset before it is permitted to issue
Configuration Request to the device immediately below that
Port.
- With a Downstream Port that does not support Link speeds greater than
  5.0 GT/s, software must wait a minimum of 100 ms before sending a
  Configuration Request to the device immediately below that Port.
- With a Downstream Port that supports Link speeds greater than
  5.0 GT/s, software must wait a minimum of 100 ms after Link training
  completes before sending a Configuration Request to the device
  immediately below that Port.

Unfortunately, ther is a compatible link down issue when NEC Corporation
uPD720200 USB 3.0 Host Controller (rev 04) is used on i.MX7D SDB board.
When add the 100ms delay just at the end of the reset.

To level up the compatibility and align with the SPEC, add the 100ms
wait after the end of the PERST# toggle and link is up to fix the link
down compatible issue when NEC uPD720200 is used on i.MX7D SDB board.

And refer to PCIe r4.0 sec 6.6.1, A component must enter the LTSSM
Detect state within 20 ms of the end of Fundamental Reset.

To level up the compatibility of i.MX8MP PCIe to support one PLEXTOR
NVME SSD device. Add one 20ms delay at the end of the PERST# toggle and
before the start of the link training for i.MX8MP PCIe.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

PCIe r4.0 sec 6.6.1, Conventional Reset.
The set of rules addresses requirements placed on the system:
To allow components to perform internal initialization, system
software must wait a specified minimum period following the
end of a Conventional Reset before it is permitted to issue
Configuration Request to the device immediately below that
Port.
- With a Downstream Port that does not support Link speeds greater than
  5.0 GT/s, software must wait a minimum of 100 ms before sending a
  Configuration Request to the device immediately below that Port.
- With a Downstream Port that supports Link speeds greater than
  5.0 GT/s, software must wait a minimum of 100 ms after Link training
  completes before sending a Configuration Request to the device
  immediately below that Port.

Unfortunately, ther is a compatible link down issue when NEC Corporation
uPD720200 USB 3.0 Host Controller (rev 04) is used on i.MX7D SDB board.
When add the 100ms delay just at the end of the reset.

To level up the compatibility and align with the SPEC, add the 100ms
wait after the end of the PERST# toggle and link is up.

So, revert the commit 079f7245 ("LF-4081 PCI: imx: wait specified
minimum period following the end of a reset") firstly.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

Without this patch, the driver sets the DSI mode to 0x08 for RM67199,
which means 'command RAM mode' as the panel data sheet indicates.
In that mode, something like screen tearing effect can be seen when
doing page flip test by using modetest.  This patch changes the DSI
mode to 0x0B for RM67199, which means 'video RAM capture mode' and
aligns to the setting of RM67191.

Fixes: ac708b5b ("MLK-24805-1: drm/panel: rm67191: Add support for rm67199")
Cc: Sandor Yu <Sandor.yu@nxp.com>
Cc: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

When running the below system suspend/resume test case on
i.MX8ulp EVK platform with the RM68200 MIPI DSI panel enabled,
DCNANO display controller power usage count and pixel clock enable
count would be unbalanced when the DRM connector's DPMS property
is changed from off to on after system resumes, if the DPMS property
is off before system suspends.  The root cause is that the
crtc_helper_funcs->mode_set_nofb() is called twice during the
procedure without crtc disablement, one at system resume stage and
one for DPMS on operation.  That means the pm_runtime_get_sync()
would be called twice at that function and pixel clock would be
enabled twice as well.  This patch introduces a flag to indicate
if the modeset is done or not to avoid the doulbe modeset so that
the reference counts are balanced.

while true; do modetest -M imx-dcnano -w 34:DPMS:3; done &
while true; do /unit_tests/SRTC/rtcwakeup.out -s 2 -m mem; done

Fixes: ce68244e ("MLK-25531-2 drm/imx: Add dcnano drm support")
Cc: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

When running the below system suspend/resume test case on
i.MX8ulp EVK platform with RM68200 MIPI DSI panel enabled,
panel register access would fail when the DRM connector's
DPMS property is changed from off to on after system resumes,
if the DPMS property is off before system suspends.
The root cause is that the bridge_funcs->mode_set() is called
twice during the procedure without bridge disablement, one at
system resume stage and one for DPMS on operation.  That means
the MIPI DPHY is not powered down during the procedure and
initialized/powered on twice.  As the PHY core driver takes
reference count for the power on operation, the second power
on operation doesn't take effect, hence the DPHY stays at
the initialization status.  This patch introduces a flag to
indicate if the modeset is done or not to avoid the doulbe
modeset so that the DPHY will be active when the panel registers
are accessed.

while true; do modetest -M imx-dcnano -w 34:DPMS:3; done &
while true; do /unit_tests/SRTC/rtcwakeup.out -s 2 -m mem; done

Fixes: 120ffd6b ("MLK-25574-4 drm/bridge: nwl-dsi: Get MIPI DSI controller and PHY ready in ->mode_set()")
Cc: Sandor Yu <Sandor.yu@nxp.com>
Reported-by: Zhang Bo <bo.zhang@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

Fix copyright format：Copyright <year> NXP

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

Fix copyright format：Copyright <year> NXP

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

Fix crash observed in VSP while trying to get link status when link is
down from kernel.

Signed-off-by: Rohit Raj <rohit.raj@nxp.com>
DPDK-3239

Currently when the device is reset, the entire DPRC container
was reset which is very inefficient because the devices within a
container will be reset multiple times.
Added support for individually resetting a device.

Signed-off-by: Diana Craciun <diana.craciun@oss.nxp.com>

The open/reset/close commands format is similar for all objects.
Currently there are multiple implementation for these commands
scattered thorugh various drivers. The code is cavsi-identical.
Create a generic implementation for the open/reset/close commands.
One of the consumer will be the VFIO driver which needs to
be able to reset a device.

Signed-off-by: Diana Craciun <diana.craciun@oss.nxp.com>

The netdev should be unregistered before we are disconnecting from the MAC/PHY
so that the dev_close callback is called and the PHY and the phylink workqueues
are actually stopped before we are disconnecting and destroying the phylink instance.

Fixes: 71947923 ("dpaa2-eth: add MAC/PHY support through phylink")
Signed-off-by: Robert-Ionut Alexa <robert-ionut.alexa@nxp.com>

After cdns DP API change, need use the correct dev for function DRM_DEV_ERROR
otherwise, there will be module driver build issue.

Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Acked-by: Robby Cai <robby.cai@nxp.com>

The regmap_config.max_register should match with
regmap_config.reg_defaults definition, otherwise:

[    5.007222] ==================================================================
[    5.014592] BUG: KASAN: slab-out-of-bounds in regcache_flat_init+0xd0/0x120
[    5.021635] Write of size 4 at addr ffff00000ab1d500 by task swapper/0/1
[    5.028397]
[    5.029954] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.10.52-03729-gd820c2b9c5b0 #824
[    5.037944] Hardware name: NXP i.MX8ULP EVK (DT)
[    5.042615] Call trace:
[    5.045142]  dump_backtrace+0x0/0x2b4
[    5.048884]  show_stack+0x18/0x24
[    5.052275]  dump_stack+0xfc/0x168
[    5.055757]  print_address_description.constprop.0+0x6c/0x488
[    5.061594]  kasan_report+0x118/0x210
[    5.065329]  __asan_store4+0x98/0xd4
[    5.068985]  regcache_flat_init+0xd0/0x120
[    5.073158]  regcache_init+0x33c/0x72c
[    5.076982]  __regmap_init+0xdf8/0x1730
[    5.080896]  __devm_regmap_init+0x70/0xc4
[    5.084980]  __devm_regmap_init_mmio_clk+0xd8/0x120
[    5.089956]  fsl_sai_probe+0x1c0/0xaf0
[    5.093784]  platform_drv_probe+0x70/0xd0
[    5.097863]  really_probe+0x148/0x704
[    5.101595]  driver_probe_device+0x78/0xec
[    5.105762]  device_driver_attach+0x118/0x120
[    5.110197]  __driver_attach+0xb0/0x190
[    5.114099]  bus_for_each_dev+0xe8/0x160
[    5.118092]  driver_attach+0x34/0x44
[    5.121736]  bus_add_driver+0x1b8/0x2c0
[    5.125641]  driver_register+0xe0/0x210
[    5.129552]  __platform_driver_register+0x80/0x90
[    5.134341]  fsl_sai_driver_init+0x1c/0x28
[    5.138512]  do_one_initcall+0xa8/0x260
[    5.142429]  kernel_init_freeable+0x2cc/0x350
[    5.146859]  kernel_init+0x14/0x12c
[    5.150420]  ret_from_fork+0x10/0x38

Fixes: 722eaf74 ("MLK-25556-7: ASoC: fsl_sai: add max_register in soc data")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Reported-by: Jason Liu <jason.hui.liu@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>

This reverts commit 1294e216.

Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <Robby.Cai@nxp.com>

This reverts commit a70a560f.

Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <Robby.Cai@nxp.com>

This reverts commit 5da3df26.

Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <Robby.Cai@nxp.com>

This reverts commit 48acce75.

Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <Robby.Cai@nxp.com>

imx6ulz has no csi. delete csi and camera nodes to avoid confusion.

Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Alice Yuan <alice.yuan@nxp.com>

imx6ulz has no pxp, so remove pxp related nodes to avoid confusion.

Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Alice Yuan <alice.yuan@nxp.com>

Consecutive runs of cplay now fails because after first
cplay the Firmware components states is not reset.

We need to send SOF_IPC_STREAM_PCM_FREE command when a stream is
closed in order to cleanup components states in Firmware.

This will cause a pipeline reset and it will put the pipeline +
components in a known state.

Reviewed-by: Peng Zhang <peng.zhang_8@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>