[C57][DTS][C57-62] Add QSPI flash support

arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts

@@ -286,6 +286,13 @@
                 IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15   0x00000021
                 /*MUTE AUDIO#*/
                 IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28		0x00000021
+                /*QSPI0B_GPIO*/
+                IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18   0x00000021
+                IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19   0x00000021
+                IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20   0x00000021
+                IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21   0x00000021
+                IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23   0x00000021
+                IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24   0x00000021
                 /*CN25 I/O*/
                 IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00	   0x00000021
             >;
@@ -360,6 +367,17 @@
             >;
         };
 
+        pinctrl_qspi0: qspi0grp {
+            fsl,pins = <
+                IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0xc6000020
+                IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0xc6000020
+                IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0xc6000020
+                IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0xc6000020
+                IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0xc6000020
+                IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0xc6000020
+            >;
+        };
+
         pinctrl_cm40_i2c: cm40i2cgrp {
             fsl,pins = <
                 IMX8QXP_ADC_IN1_M40_I2C0_SDA	0x0600004c
@@ -765,6 +783,20 @@ gpio5: &lsio_gpio5 {
     phy-reset-duration = <2>;
 };
 
+&flexspi0 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_qspi0>;
+    status = "okay";
+
+    flash0: mx25u6435f@0{
+        reg = <0>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "macronix,mx25u6435f", "jedec,spi-nor";
+        spi-max-frequency = <80000000>;
+    };
+};
+
 &cm40_intmux {
     status = "okay";
 };