[C57][DTS][C57-53] Add CortexM4 UART

arch/arm64/boot/dts/seco/seco-imx8qxp-c57.dts

@@ -42,6 +42,7 @@
         serial1 = &lpuart1;
         serial2 = &lpuart2;
         serial3 = &lpuart3;
+        serial4 = &cm40_lpuart;
         mmc0 = &usdhc1;
         mmc1 = &usdhc2;
         i2c4 = &cm40_i2c;
@@ -295,6 +296,10 @@
                 IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24   0x00000021
                 /*CN25 I/O*/
                 IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00	   0x00000021
+                /*UART0 CTS/RTS*/
+                IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B	0x16000020
+                IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B	0x16000020
+
             >;
         };
 
@@ -324,6 +329,14 @@
                 IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX	0x06000020
             >;
         };
+
+		pinctrl_cm40_lpuart: cm40_lpuartgrp {
+			fsl,pins = <
+				IMX8QXP_ADC_IN2_M40_UART0_RX		0x06000020
+				IMX8QXP_ADC_IN3_M40_UART0_TX		0x06000020
+			>;
+		};
+
         pinctrl_fec1: fec1grp {
             fsl,pins = <
                 IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0
@@ -711,6 +724,13 @@ gpio5: &lsio_gpio5 {
     status = "okay";
 };
 
+&cm40_lpuart {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_cm40_lpuart>;
+    status = "okay";
+};
+
+
 &lpspi2 {
     fsl,spi-num-chipselects = <1>;
     cs-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;