[C61][DTO][EDP] sn65dsi86 remove explicit declaration of the clock

If we look at the hw design of the board the SN65DSI86 should use the external clock REFCLK.
However, for some reasons (maybe also an error), the corresponding clock generator SI5351A
has never been declared even in the old kernels used for the signal integrity and emission test;
so no REFCLK is present in the corresponding SN65DSI86 pin.
What happen is that the SN65DSI86 automatically detect that there is no clock in the REFCLK
pin and so try to get DP PLL from the DSI DACP/N pins, even if inside the driver the code try to
set the clock based on the "clocks = <&osc_27m>" parameter that explicit a REFCLK.

Somehow this condition work most of the time, but there are some boards where this condition bring to an error during the "Link training" of the edp:
     [drm:ti_sn_bridge_enable] *ERROR* Link training failed, link is off

With the hw team has been decided to just remove the declaration of the REFCLK in the dts so that
the driver correctly set the refclk frequency (ti_sn_bridge_set_refclk_freq function) and fix the "link training" error.
This decision is to not change the condition of the board compared to the signal integrity and the emission test

arch/arm64/boot/dts/seco/overlays/seco-imx8mm-c61-video-sn65dsi86-overlay.dts

@@ -150,7 +150,6 @@
 				pd-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
 				bkl-gpios = <&pca6416_20 5 GPIO_ACTIVE_HIGH>;
 				vcc-supply = <&reg_bkl_on>;
-				clocks = <&osc_27m>;
 				dsi,max-lanes = <4>;
 				dsi,max-rate = <2500>;
 				dsi,mode-flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM)>;