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Commit c1c1e8b0 authored by Liu Ying's avatar Liu Ying Committed by Leonard Crestez
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MLK-17022 drm/panel: panel-simple: Correct JDI TX26D202VM0BWA panel display timing flags


The JDI TX26D202VM0BWA panel works in data enable(DE) mode.
Apparently, the panel's data enable signal is active high
according to the panel spec.  This patch corrects the DE
signal polarity from active low to active high.

Signed-off-by: default avatarLiu Ying <victor.liu@nxp.com>
(cherry picked from commit ed0230ec)
parent e033f243
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...@@ -1423,7 +1423,7 @@ static const struct display_timing jdi_tx26d202vm0bwa_timing = { ...@@ -1423,7 +1423,7 @@ static const struct display_timing jdi_tx26d202vm0bwa_timing = {
.vfront_porch = { 3, 5, 10 }, .vfront_porch = { 3, 5, 10 },
.vback_porch = { 2, 5, 10 }, .vback_porch = { 2, 5, 10 },
.vsync_len = { 5, 5, 5 }, .vsync_len = { 5, 5, 5 },
.flags = DISPLAY_FLAGS_DE_LOW, .flags = DISPLAY_FLAGS_DE_HIGH,
}; };
static const struct panel_desc jdi_tx26d202vm0bwa = { static const struct panel_desc jdi_tx26d202vm0bwa = {
......
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