[D18][DTBO] Adapt VIDEO_PLL1 rate in 10.1" display devicetree overlay

To get a pixelclock close to the requested 71.1Mhz, the
VIDEO_PLL1's rate is requested to be 14 times the pixel clock.
Here the assigned-clock and assigned-clock-rate is used.
This is not completly correct, as according to the documentation, this
should only by used, when a clock only drives one child, but
NXP already uses this, for the PLLs.
This leads to a reconfiguration during boot, as first the settings from
the CCM are used and later, when the panel is probed, the new setting is
applied, which is OK (needs recheck if it comes to multiple displays,
though).

[MODV-102]

arch/arm64/boot/dts/seco/overlays/seco-imx8mp-d18-lvds-g101ean02-overlay.dts

@@ -14,6 +14,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include "../include/imx8mp-pinfunc.h"
+#include <dt-bindings/clock/imx8mp-clock.h>
 
 /dts-v1/;
 /plugin/;
@@ -40,6 +41,14 @@
 				enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 				backlight = <&pwm_backlight>;
 
+				/* Change the 'parent' PLL to pixel clock * 14.
+				   If possible 14 seems to be a good multiplier,
+				   as the PLL also drives the ldb which needs
+				   7 times the pixel clock as input.
+				*/
+				assigned-clocks = <&clk IMX8MP_VIDEO_PLL1>;
+				assigned-clock-rates = <995400000>;
+
 				panel-timing {
 					clock-frequency = <71100000>;
 					hactive = <1280>;