[MX8MP][D18] Add additional PLL setpoint at 995Mhz for 71.1Mhz pixelclock

The 10.1" display for modular vision requires a display clock of
71.1Mhz. This adds a new setpoint to the pll at 14 times the pixel clock
to allow good matching of the generated clock.

[MODV-102]

drivers/clk/imx/clk-pll14xx.c

@@ -57,8 +57,15 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
 	PLL_1416X_RATE(600000000U,  300, 3, 2),
 };
 
+/* According to refmanual V1.0 the formula for the PLL is:
+	(( m + k/65536 ) * Fin ) / ( p * pow(2, s))
+	Fin is 24Mhz (mx8mp and mx8mm)
+	The PLL_1443X_RATE macro parameters are:
+	rate, m , p s, k
+*/  
 static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
 	PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
+	PLL_1443X_RATE(995400000U, 166, 2, 1, -6554),
 	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
 	PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
 	PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),