dts:genio: Add pinfunc file

Header file with defined pin functions was added, interrupt pin defines were moved inside and will be removed once the overlays in meta-seconorth-mtk layera re updated as well

arch/arm64/boot/dts/seco/seco-genio-common.dtsi

@@ -7,8 +7,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
 #include <dt-bindings/usb/pd.h>
-#include "seco-genio-irq.h"
-
+#include "seco-genio-pinfunc.h"
 
 / {	
 	aliases {
@@ -21,7 +20,7 @@ aliases {
 	backlight_lcd0: backlight-lcd0 {
 		compatible = "pwm-backlight";
 		pwms = <&disp_pwm0 0 500000>;
-		enable-gpios = <&pio 25 GPIO_ACTIVE_HIGH>;// DSI0_LCM_RST, Y9
+		enable-gpios = <LVDS0_BKLT_EN GPIO_ACTIVE_HIGH>;// DSI0_LCM_RST, Y9
 		brightness-levels = <0 1023>;
 		num-interpolated-steps = <1023>;
 		default-brightness-level = <576>;
@@ -560,7 +559,7 @@ &afe {
 &eth {
 	phy-mode ="rgmii-rxid";
 	phy-handle = <&ethernet_phy0>;
-	snps,reset-gpio = <&pio 147 GPIO_ACTIVE_HIGH>;
+	snps,reset-gpio = <ENET0_RST_1V8 GPIO_ACTIVE_HIGH>;
 	snps,reset-delay-us = <0 10000 10000>;
 	mediatek,tx-delay-ps = <2030>;
 	mediatek,mac-wol;
@@ -1164,7 +1163,7 @@ it5205fn: it5205fn@48 {
 	lvds_bridge: lvds-bridge@2c {
 		compatible = "ti,sn65dsi84";
 		reg = <0x2c>;
-		enable-gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
+		enable-gpios = <LVDS_EN GPIO_ACTIVE_HIGH>;
 		status = "disabled";
 
 		ports {
@@ -1230,7 +1229,7 @@ stm32: stm32@40 {
 		#gpio-cells = <2>;
 		ngpios =/bits/ 16  <STM32_NGPIOS>;
 		interrupt-parent = <&pio>;
-		interrupts = <13 IRQ_TYPE_EDGE_FALLING>;// IRQ from STM32 to CPU
+		interrupts = <EC_IRQ_OD_PIN IRQ_TYPE_EDGE_FALLING>;// IRQ from STM32 to CPU
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		status = "okay";
@@ -1461,7 +1460,7 @@ &mmc1 {
 	sd-uhs-sdr104;
 	no-mmc;
 	no-sdio;
-	cd-gpios = <&pio 2 GPIO_ACTIVE_LOW>;
+	cd-gpios = <SDIO_CD GPIO_ACTIVE_LOW>;
 	//vmmc-supply = <&mt6359_vpa_buck_reg>;
 	//vqmmc-supply = <&mt6359_vsim1_ldo_reg>;
 	//vmmc-supply = <&reg_3v3_run>;
@@ -1519,7 +1518,7 @@ &mt6359_vcn18_ldo_reg {
 */
 
 &wifi_pwrseq {
-	reset-gpios = <&stm32 38 GPIO_ACTIVE_LOW>;
+	reset-gpios = <WIFI_PWRDWN_1V8 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
@@ -1555,14 +1554,14 @@ &spi0 {
 	#address-cells = <1>;
 	#size-cells = <0>;
 	status = "disabled";
-	cs-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
+	cs-gpios = <CAN_CS GPIO_ACTIVE_LOW>;
 	
 	can0: can@0 {
 		compatible = "microchip,mcp2518fd";
 		reg = <0>;
 		clocks = <&can_clk>;
 		spi-max-frequency = <5000000>;
-		interrupts-extended = <&pio 73 IRQ_TYPE_LEVEL_LOW>;
+		interrupts-extended = <CAN_INT IRQ_TYPE_LEVEL_LOW>;
 		vdd-supply = <&reg_3v3_run>;
 		xceiver-supply = <&reg_3v3_run>;
 	};

arch/arm64/boot/dts/seco/seco-genio-pinfunc.h

+/*
+ * Copyright 2024 SECO Northern Europe GmbH
+ */
+
+#ifndef __DTS_GENIO_PINFUNC_H
+#define __DTS_GENIO_PINFUNC_H
+
+/* 
+    STM32 pins 
+*/
+
+/* Interrupt pins */
+
+#define STM32_NGPIOS 43
+#define STM32_IRQ_BASE STM32_NGPIOS
+#define STM32_IRQ_RTC (STM32_IRQ_BASE + 0)
+#define STM32_IRQ_SMB (STM32_IRQ_BASE + 1)
+#define STM32_IRQ_CPU (STM32_IRQ_BASE + 2)
+#define STM32_IRQ_GPIO6 (STM32_IRQ_BASE + 3)
+
+/* GPIO pins */
+
+#define SMARC_GPIO4_PIN 4
+#define SMARC_GPIO4 &stm32 SMARC_GPIO4_PIN
+
+#define SMARC_GPIO5_PIN 5
+#define SMARC_GPIO5 &stm32 SMARC_GPIO5_PIN
+
+#define SMARC_GPIO6_PIN 6
+#define SMARC_GPIO6 &stm32 SMARC_GPIO6_PIN
+#define SMARC_GPIO6_IRQ_PIN STM32_IRQ_GPIO6
+#define SMARC_GPIO6_IRQ &stm32 SMARC_GPIO6_IRQ_PIN
+
+#define SMARC_GPIO7_PIN 7
+#define SMARC_GPIO7 &stm32 SMARC_GPIO7_PIN
+
+#define SMARC_GPIO8_PIN 8
+#define SMARC_GPIO8 &stm32 SMARC_GPIO8_PIN
+
+#define SMARC_GPIO9_PIN 9
+#define SMARC_GPIO9 &stm32 SMARC_GPIO9_PIN
+
+#define SMARC_GPIO10_PIN 10
+#define SMARC_GPIO10 &stm32 SMARC_GPIO10_PIN
+
+#define SMARC_GPIO11_PIN 11
+#define SMARC_GPIO11 &stm32 SMARC_GPIO11_PIN
+
+#define SMARC_GPIO12_PIN 12
+#define SMARC_GPIO12 &stm32 SMARC_GPIO12_PIN
+
+#define SMARC_GPIO13_PIN 13
+#define SMARC_GPIO13 &stm32 SMARC_GPIO13_PIN
+
+#define USB0_EN_OC_PIN 20
+#define USB0_EN_OC &stm32 USB0_EN_OC_PIN
+
+#define USB1_EN_OC_PIN 21
+#define USB1_EN_OC &stm32 USB1_EN_OC_PIN
+
+#define USB3_EN_OC_PIN 23
+#define USB3_EN_OC &stm32 USB3_EN_OC_PIN
+
+#define USB_HUB_RST_1V8_PIN 26
+#define USB_HUB_RST_1V8_OC &stm32 USB_HUB_RST_1V8_PIN
+
+#define WIFI_CLK_EN_PIN 37
+#define WIFI_CLK_EN &stm32 WIFI_CLK_EN_PIN
+
+#define WIFI_PWRDWN_1V8_PIN 38
+#define WIFI_PWRDWN_1V8 &stm32 WIFI_PWRDWN_1V8_PIN
+
+#define BATLOW_PIN 39
+#define BATLOW &stm32 BATLOW_PIN
+
+#define CHARGING_PIN 40
+#define CHARGING &stm32 CHARGING_PIN
+
+#define CHARGER_PRSNT_PIN 41
+#define CHARGER_PRSNT &stm32 CHARGER_PRSNT_PIN
+
+#define RESET_OUT_PIN 42
+#define RESET_OUT &stm32 RESET_OUT_PIN
+
+/* 
+    Genio pins 
+*/
+
+#define SDIO_CD_PIN 2
+#define SDIO_CD &pio SDIO_CD_PIN
+
+#define WIFI_DISABLE_PIN 3
+#define WIFI_DISABLE &pio WIFI_DISABLE_PIN
+
+#define SDIO_PWR_EN_PIN 4
+#define SDIO_PWR_EN &pio SDIO_PWR_EN_PIN
+
+#define BT_IRQ_PIN 5
+#define BT_IRQ &pio BT_IRQ_PIN
+
+#define TPM_RST_PIN 6
+#define TPM_RST &pio TPM_RST_PIN
+
+#define I2C_PIRQ_PIN 7
+#define I2C_PIRQ &pio I2C_PIRQ_PIN
+
+#define LVDS_EN_PIN 12
+#define LVDS_EN &pio LVDS_EN_PIN
+
+#define EC_IRQ_OD_PIN 13
+#define EC_IRQ_OD &pio EC_IRQ_OD_PIN
+
+#define CPU_IRQ_PIN 15
+#define CPU_IRQ &pio CPU_IRQ_PIN
+
+#define MT6319_INT_PIN 16
+#define MT6319_INT &pio MT6319_INT_PIN
+
+#define EDP1_HPD_PIN 17
+#define EDP1_HPD &pio EDP1_HPD_PIN
+
+#define SMARC_GPIO0_PIN 18
+#define SMARC_GPIO0 &pio SMARC_GPIO0_PIN
+#define SMARC_CAM0_PWR SMARC_GPIO0
+
+#define SMARC_GPIO2_PIN 19
+#define SMARC_GPIO2 &pio SMARC_GPIO2_PIN
+#define SMARC_CAM0_RST SMARC_GPIO2
+
+#define SMARC_GPIO1_PIN 20
+#define SMARC_GPIO1 &pio SMARC_GPIO1_PIN
+#define SMARC_CAM1_PWR SMARC_GPIO1
+
+#define SMARC_GPIO3_PIN 21
+#define SMARC_GPIO3 &pio SMARC_GPIO3_PIN
+#define SMARC_CAM1_RST SMARC_GPIO3
+
+#define LVDS0_BKLT_EN_PIN 25
+#define LVDS0_BKLT_EN &pio LVDS0_BKLT_EN_PIN
+
+#define LVDS0_VDD_EN_PIN 26
+#define LVDS0_VDD_EN &pio LVDS0_VDD_EN_PIN
+
+#define LCD1_BKLT_EN_PIN 27
+#define LCD1_BKLT_EN &pio LCD1_BKLT_EN_PIN
+
+#define LCD1_VDD_EN_PIN 28
+#define LCD1_VDD_EN &pio LCD1_VDD_EN_PIN
+
+#define LVDS0_BKLT_PWM_PIN 29
+#define LVDS0_BKLT_PWM &pio LVDS0_BKLT_PWM_PIN
+
+#define LCD1_BKLT_PWM_PIN 30
+#define LCD1_BKLT_PWM &pio LCD1_BKLT_PWM_PIN
+
+#define SER1_TX_PIN 31
+#define SER1_TX &pio SER1_TX_PIN
+
+#define SER1_RX_PIN 32
+#define SER1_RX &pio SER1_RX_PIN
+
+#define SER0_TX_PIN 33
+#define SER0_TX &pio SER0_TX_PIN
+
+#define SER0_RX_PIN 34
+#define SER0_RX &pio SER0_RX_PIN
+
+#define SER0_RTS_PIN 35
+#define SER0_RTS &pio SER0_RTS_PIN
+
+#define SER0_CTS_PIN 36
+#define SER0_CTS &pio SER0_CTS_PIN
+
+#define JTAG_TMS_PIN 37
+#define JTAG_TMS &pio JTAG_TMS_PIN
+
+#define JTAG_TCK_PIN 38
+#define JTAG_TCK &pio JTAG_TCK_PIN
+
+#define JTAG_TDI_PIN 39
+#define JTAG_TDI &pio JTAG_TDI_PIN
+
+#define JTAG_TDO_PIN 40
+#define JTAG_TDO &pio JTAG_TDO_PIN
+
+#define JTAG_TRST_PIN 41
+#define JTAG_TRST &pio JTAG_TRST_PIN
+
+#define KPCOL0_PIN 42
+#define KPCOL0 &pio KPCOL0_PIN
+
+#define KPCOL1_PIN 43
+#define KPCOL1 &pio KPCOL1_PIN
+
+#define KPROW0_PIN 44
+#define KPROW0 &pio KPROW0_PIN
+
+#define KPROW1_PIN 45
+#define KPROW1 &pio KPROW1_PIN
+
+#define DP0_HPD_PIN 46
+#define DP0_HPD &pio DP0_HPD_PIN
+
+#define EXT_PCIE_WAKE_PIN 47
+#define EXT_PCIE_WAKE &pio EXT_PCIE_WAKE_PIN
+
+#define PCIE_A_RST_PIN 48
+#define PCIE_A_RST &pio PCIE_A_RST_PIN
+
+#define PCIE_A_CKREQ_PIN 49
+#define PCIE_A_CKREQ &pio PCIE_A_CKREQ_PIN
+
+#define HDMI_HPD_PIN 51
+#define HDMI_HPD &pio HDMI_HPD_PIN
+
+#define HDMI_CTRL_CK_PIN 53
+#define HDMI_CTRL_CK &pio HDMI_CTRL_CK_PIN
+
+#define HDMI_CTRL_DAT_PIN 54
+#define HDMI_CTRL_DAT &pio HDMI_CTRL_DAT_PIN
+
+#define I2C0_SCL_PIN 55
+#define I2C0_SCL &pio I2C0_SCL_PIN
+
+#define I2C0_SDA_PIN 56
+#define I2C0_SDA &pio I2C0_SDA_PIN
+
+#define I2C1_SCL_PIN 57
+#define I2C1_SCL &pio I2C1_SCL_PIN
+
+#define I2C1_SDA_PIN 58
+#define I2C1_SDA &pio I2C1_SDA_PIN
+
+#define I2C2_SCL_PIN 59
+#define I2C2_SCL &pio I2C2_SCL_PIN
+
+#define I2C2_SDA_PIN 60
+#define I2C2_SDAL &pio I2C2_SDA_PIN
+
+#define I2C3_SCL_PIN 61
+#define I2C3_SCL &pio I2C3_SCL_PIN
+
+#define I2C3_SDA_PIN 62
+#define I2C3_SDA &pio I2C3_SDA_PIN
+
+#define I2C_GP_CK_PIN 63
+#define I2C_GP_CK &pio I2C_GP_CK_PIN
+
+#define I2C_GP_DAT_PIN 64
+#define I2C_GP_DAT &pio I2C_GP_DAT_PIN
+
+#define I2C5_SCL_PIN 65
+#define I2C5_SCL &pio I2C5_SCL_PIN
+
+#define I2C5_SDA_PIN 66
+#define I2C5_SDA &pio I2C5_SDA_PIN
+
+#define I2C_PM_CK_PIN 67
+#define I2C_PM_CK &pio I2C_PM_CK_PIN
+
+#define I2C_PM_DAT_PIN 68
+#define I2C_PM_DAT &pio I2C_PM_DAT_PIN
+
+#define CAN_CS_PIN 69
+#define CAN_CS &pio CAN_CS_PIN
+
+#define CAN_SCK_PIN 70
+#define CAN_SCK &pio CAN_SCK_PIN
+
+#define CAN_SDI_PIN 71
+#define CAN_SDI &pio CAN_SDI_PIN
+
+#define CAN_SDO_PIN 72
+#define CAN_SDO &pio CAN_SDO_PIN
+
+#define CAN_INT_PIN 73
+#define CAN_INT &pio CAN_INT_PIN
+
+#define SPI0_CS0_PIN 75
+#define SPI0_CS0 &pio SPI0_CS0_PIN
+
+#define SPI0_CK_PIN 76
+#define SPI0_CK &pio SPI0_CK_PIN
+
+#define SPI0_DO_PIN 77
+#define SPI0_DO &pio SPI0_DO_PIN
+
+#define SPI0_DIN_PIN 78
+#define SPI0_DIN &pio SPI0_DIN_PIN
+
+#define UART2_TX_PIN 79
+#define UART2_TX &pio UART2_TX_PIN
+
+#define UART2_RX_PIN 80
+#define UART2_RX &pio UART2_RX_PIN
+
+#define UART2_RTS_PIN 81
+#define UART2_RTS &pio UART2_RTS_PIN
+
+#define UART2_CTS_PIN 82
+#define UART2_CTS &pio UART2_CTS_PIN
+
+#define USB0_OTG_ID_PIN 83
+#define USB0_OTG_ID &pio USB0_OTG_ID_PIN
+
+#define USB0_VBUS_1V8_PIN 85
+#define USB0_VBUS_1V8 &pio USB0_VBUS_1V8_PIN
+
+#define USB3_OTG_ID_PIN 86
+#define USB3_OTG_ID &pio USB3_OTG_ID_PIN
+
+#define USB3_VBUS_1V8_PIN 88
+#define USB3_VBUS_1V8 &pio USB3_VBUS_1V8_PIN
+
+#define PWRAP_SPI_CSN_PIN 92
+#define PWRAP_SPI_CSN &pio PWRAP_SPI_CSN_PIN
+
+#define PWRAP_SPI_CK_PIN 93
+#define PWRAP_SPI_CK &pio PWRAP_SPI_CK_PIN
+
+#define PWRAP_SPI_MO_PIN 94
+#define PWRAP_SPI_MO &pio PWRAP_SPI_MO_PIN
+
+#define PWRAP_SPI_MI_PIN 95
+#define PWRAP_SPI_MI &pio PWRAP_SPI_MI_PIN
+
+#define PMIC_SRCLKENA0_PIN 96
+#define PMIC_SRCLKENA0 &pio PMIC_SRCLKENA0_PIN
+
+#define PMIC_SRCLKENA1_PIN 97
+#define PMIC_SRCLKENA1 &pio PMIC_SRCLKENA1_PIN
+
+#define SCP_VREQ_VAO_PIN 98
+#define SCP_VREQ_VAO &pio SCP_VREQ_VAO_PIN
+
+#define PMIC_RTC32K_CK_PIN 99
+#define PMIC_RTC32K_CK &pio PMIC_RTC32K_CK_PIN
+
+#define PMIC_WATCHDOG_PIN 100
+#define PMIC_WATCHDOG &pio PMIC_WATCHDOG_PIN
+
+#define AUD_CLK_MOSI_PIN 101
+#define AUD_CLK_MOSI &pio AUD_CLK_MOSI_PIN
+
+#define AUD_SYNC_MOSI_PIN 102
+#define AUD_SYNC_MOSI &pio AUD_SYNC_MOSI_PIN
+
+#define AUD_DAT_MOSI0_PIN 103
+#define AUD_DAT_MOSI0 &pio AUD_DAT_MOSI0_PIN
+
+#define AUD_DAT_MOSI1_PIN 104
+#define AUD_DAT_MOSI1 &pio AUD_DAT_MOSI1_PIN
+
+#define AUD_DAT_MISO0_PIN 105
+#define AUD_DAT_MISO0 &pio AUD_DAT_MISO0_PIN
+
+#define AUD_DAT_MISO1_PIN 106
+#define AUD_DAT_MISO1 &pio AUD_DAT_MISO1_PIN
+
+#define I2S0_CK_PIN 108
+#define I2S0_CK &pio I2S0_CK_PIN
+
+#define I2S0_LRCK_PIN 109
+#define I2S0_LRCK &pio I2S0_LRCK_PIN
+
+#define I2S0_SDIN_PIN 110
+#define I2S0_SDIN &pio I2S0_SDIN_PIN
+
+#define I2SO2_MCK_PIN 114
+#define I2SO2_MCK &pio I2SO2_MCK_PIN
+
+#define I2S2_CK_PIN 115
+#define I2S2_CK &pio I2S2_CK_PIN
+
+#define I2S2_LRCK_PIN 116
+#define I2S2_LRCK &pio I2S2_LRCK_PIN
+
+#define I2S2_SDOUT_PIN 117
+#define I2S2_SDOUT &pio I2S2_SDOUT_PIN
+
+#define PCM_CLK_PIN 121
+#define PCM_CLK &pio PCM_CLK_PIN
+
+#define PCM_SYNC_PIN 122
+#define PCM_SYNC &pio PCM_SYNC_PIN
+
+#define PCM_DO_PIN 123
+#define PCM_DO &pio PCM_DO_PIN
+
+#define PCM_DI_PIN 124
+#define PCM_DI &pio PCM_DI_PIN
+
+#define ESPI_CK_PIN 125
+#define ESPI_CK &pio ESPI_CK_PIN
+
+#define ESPI_CS0_PIN 126
+#define ESPI_CS0 &pio ESPI_CS0_PIN
+
+#define ESPI_IO_0_PIN 127
+#define ESPI_IO_0 &pio ESPI_IO_0_PIN
+
+#define ESPI_IO_1_PIN 128
+#define ESPI_IO_1 &pio ESPI_IO_1_PIN
+
+#define ESPI_IO_2_PIN 129
+#define ESPI_IO_2 &pio ESPI_IO_2_PIN
+
+#define ESPI_IO_3_PIN 130
+#define ESPI_IO_3 &pio ESPI_IO_3_PIN
+
+#define ENET0_TD3_PIN 131
+#define ENET0_TD3 &pio ENET0_TD3_PIN
+
+#define ENET0_TD2_PIN 132
+#define ENET0_TD2 &pio ENET0_TD2_PIN
+
+#define ENET0_TD1_PIN 133
+#define ENET0_TD1 &pio ENET0_TD1_PIN
+
+#define ENET0_TD0_PIN 134
+#define ENET0_TD0 &pio ENET0_TD0_PIN
+
+#define ENET0_RD3_PIN 135
+#define ENET0_RD3 &pio ENET0_RD3_PIN
+
+#define ENET0_RD2_PIN 136
+#define ENET0_RD2 &pio ENET0_RD2_PIN
+
+#define ENET0_RD1_PIN 137
+#define ENET0_RD1 &pio ENET0_RD1_PIN
+
+#define ENET0_RD0_PIN 138
+#define ENET0_RD0 &pio ENET0_RD0_PIN
+
+#define ENET0_TXC_PIN 139
+#define ENET0_TXC &pio EENET0_TXC_PIN
+
+#define ENET0_RXC_PIN 140
+#define ENET0_RXC &pio ENET0_RXC_PIN
+
+#define ENET0_RX_CTL_PIN 141
+#define ENET0_RX_CTL &pio ENET0_RX_CTL_PIN
+
+#define ENET0_TX_CTL_PIN 142
+#define ENET0_TX_CTL &pio ENET0_TX_CTL_PIN
+
+#define ENET0_MDC_PIN 143
+#define ENET0_MDC &pio ENET0_MDC_PIN
+
+#define ENET0_MDIO_PIN 144
+#define ENET0_MDIO &pio ENET0_MDIO_PIN
+
+#define ENET0_RST_1V8_PIN 147
+#define ENET0_RST_1V8 &pio ENET0_RST_1V8_PIN
+
+#define ENET0_INT_1V8_PIN 148
+#define ENET0_INT_1V8 &pio ENET0_INT_1V8_PIN
+
+#define SER3_TX_PIN 149
+#define SER3_TX &pio SER3_TX_PIN
+
+#define SER3_RX_PIN 150
+#define SER3_RX &pio SER3_RX_PIN
+
+#define EMMC_DAT7_PIN 151
+#define EMMC_DAT7 &pio EMMC_DAT7_PIN
+
+#define EMMC_DAT6_PIN 152
+#define EMMC_DAT6 &pio EMMC_DAT6_PIN
+
+#define EMMC_DAT5_PIN 153
+#define EMMC_DAT5 &pio EMMC_DAT5_PIN
+
+#define EMMC_DAT4_PIN 154
+#define EMMC_DAT4 &pio EMMC_DAT4_PIN
+
+#define EMMC_RST_PIN 155
+#define EMMC_RST &pio EMMC_RST_PIN
+
+#define EMMC_CMD_PIN 156
+#define EMMC_CMD &pio EMMC_CMD_PIN
+
+#define EMMC_CLK_PIN 157
+#define EMMC_CLK &pio EMMC_CLK_PIN
+
+#define EMMC_DAT3_PIN 158
+#define EMMC_DAT3 &pio EMMC_DAT3_PIN
+
+#define EMMC_DAT2_PIN 159
+#define EMMC_DAT2 &pio EMMC_DAT2_PIN
+
+#define EMMC_DAT1_PIN 160
+#define EMMC_DAT1 &pio EMMC_DAT1_PIN
+
+#define EMMC_DAT0_PIN 161
+#define EMMC_DAT0 &pio EMMC_DAT0_PIN
+
+#define EMMC_DSL_PIN 162
+#define EMMC_DSL &pio EMMC_DSL_PIN
+
+#define SDIO_CMD_PIN 163
+#define SDIO_CMD &pio SDIO_CMD_PIN
+
+#define SDIO_CK_PIN 164
+#define SDIO_CK &pio SDIO_CK_PIN
+
+#define SDIO_D0_PIN 165
+#define SDIO_D0 &pio SDIO_D0_PIN
+
+#define SDIO_D1_PIN 166
+#define SDIO_D1 &pio SDIO_D1_PIN
+
+#define SDIO_D2_PIN 167
+#define SDIO_D2 &pio SDIO_D2_PIN
+
+#define SDIO_D3_PIN 168
+#define SDIO_D3 &pio SDIO_D3_PIN
+
+#define MSDC2_CMD_PIN 169
+#define MSDC2_CMD &pio MSDC2_CMD_PIN
+
+#define MSDC2_CLK_PIN 170
+#define MSDC2_CLK &pio MSDC2_CLK_PIN
+
+#define MSDC2_DAT0_PIN 171
+#define MSDC2_DAT0 &pio MSDC2_DAT0_PIN
+
+#define MSDC2_DAT1_PIN 172
+#define MSDC2_DAT1 &pio MSDC2_DAT1_PIN
+
+#define MSDC2_DAT2_PIN 173
+#define MSDC2_DAT2 &pio MSDC2_DAT2_PIN
+
+#define MSDC2_DAT3_PIN 174
+#define MSDC2_DAT3 &pio MSDC2_DAT3_PIN
+
+#define SPMI_M_SCL_PIN 175
+#define SPMI_M_SCL &pio SPMI_M_SCL_PIN
+
+#define SPMI_M_SDA_PIN 176
+#define SPMI_M_SDA &pio SPMI_M_SDA_PIN
+
+#endif /* __DTS_GENIO_PINFUNC_H */