dts:panel: Added optional panel-dt node for lq057q3dc12

Added an optional node with panel-dt settings for the
lq057q3dc12.

BCS 746-000951

arch/arm64/boot/dts/seconorth/lq057q3dc12.dtsi

@@ -2,7 +2,56 @@
  * Copyright 2022 SECO Northern Europe GmbH
  */
 
+#define USE_PANEL_DT 0
+
 / {
+#if USE_PANEL_DT
+	panel_lvds: panel {
+		compatible = "seco,panel-dt";
+		label = "Sharp LQ057Q3DC12";
+		status = "okay";
+
+		width-mm = <144>;
+		height-mm = <105>;
+		rotation = <0>;
+		data-mapping = "vesa-24";
+		bus-format = <0x1012>; /* MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA */
+		bits-per-color = <6>;
+
+		power-supply = <&reg_3v3>;
+		backlight = <&backlight>;
+		enable-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
+
+		panel-timing {
+			/*
+			 * The display supports VGA and QVGA modes. In QVGA a pxl_clk of
+			 * about 6.3 MHz is required. Unfortunately, the LVDS receiver
+			 * chip doesn't support clocks below 20 MHz. Therefore the lower
+			 * clock of ~ 6.3 MHz can't be used to drive the display.
+			 *
+			 * @TODO: Further investigation into the correct timings for
+			 * the higher clock rate is required.
+			 */
+			clock-frequency = <25180000>;
+			hactive = <320>;
+			vactive = <240>;
+			hfront-porch = <40>;
+			hsync-len = <20>;
+			hback-porch = <40>;
+			vfront-porch = <15>;
+			vsync-len = <4>;
+			vback-porch = <7>;
+		};
+
+		/* delay */
+
+		port {
+			panel_lvds_in: endpoint {
+				remote-endpoint = <&lvds_out>;
+			};
+		};
+	};
+#else
 	panel_lvds: panel {
 		status = "okay";
 		compatible = "panel-lvds";
@@ -39,6 +88,7 @@ panel_lvds_in: endpoint {
 			};
 		};
 	};
+#endif
 };
 
 &backlight {