dts:mc3: Fixed the clock of the LVDS panel

The LVDS receiver requires an input clock of at least 20 MHz.
Since the display supports VGA and QVGA, the higher clock (for VGA)
is used for now.

Note: Further work on the display timings is required.

BCS 746-000951
BCS 746-000944

arch/arm64/boot/dts/seconorth/mc3.dtsi

@@ -136,7 +136,16 @@ panel_lvds: panel {
 		enable-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
 
 		panel-timing {
-			clock-frequency = <6368040>;
+			/*
+			 * The display supports VGA and QVGA modes. In QVGA a pxl_clk of
+			 * about 6.3 MHz is required. Unfortunately, the LVDS receiver
+			 * chip doesn't support clocks below 20 MHz. Therefore the lower
+			 * clock of ~ 6.3 MHz can't be used to drive the display.
+			 *
+			 * @TODO: Further investigation into the correct timings for
+			 * the higher clock rate is required.
+			 */
+			clock-frequency = <25180000>;
 			hactive = <320>;
 			vactive = <240>;
 			hfront-porch = <40>;