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  1. Jan 25, 2017
    • Geert Uytterhoeven's avatar
      net: phy: leds: Clear phy_num_led_triggers on failure to avoid crash · 8a87fca8
      Geert Uytterhoeven authored
      
      phy_attach_direct() ignores errors returned by
      phy_led_triggers_register(). I think that's OK, as LED triggers can be
      considered a non-critical feature.
      
      However, this causes problems later:
        - phy_led_trigger_change_speed() will access the array
          phy_device.phy_led_triggers, which has been freed in the error path
          of phy_led_triggers_register(), which may lead to a crash.
      
        - phy_led_triggers_unregister() will access the same array, leading to
          crashes during s2ram or poweroff, like:
      
      	Unable to handle kernel NULL pointer dereference at virtual address
      	00000000
      	...
      	[<c04116d4>] (__list_del_entry_valid) from [<c05e8948>] (led_trigger_unregister+0x34/0xcc)
      	[<c05e8948>] (led_trigger_unregister) from [<c05336c4>] (phy_led_triggers_unregister+0x28/0x34)
      	[<c05336c4>] (phy_led_triggers_unregister) from [<c0531d44>] (phy_detach+0x30/0x74)
      	[<c0531d44>] (phy_detach) from [<c0538bdc>] (sh_eth_close+0x64/0x9c)
      	[<c0538bdc>] (sh_eth_close) from [<c04d4ce0>] (dpm_run_callback+0x48/0xc8)
      
          or:
      
      	list_del corruption. prev->next should be dede6540, but was 2e323931
      	------------[ cut here ]------------
      	kernel BUG at lib/list_debug.c:52!
      	...
      	[<c02f6d70>] (__list_del_entry_valid) from [<c0425168>] (led_trigger_unregister+0x34/0xcc)
      	[<c0425168>] (led_trigger_unregister) from [<c03a05a0>] (phy_led_triggers_unregister+0x28/0x34)
      	[<c03a05a0>] (phy_led_triggers_unregister) from [<c039ec04>] (phy_detach+0x30/0x74)
      	[<c039ec04>] (phy_detach) from [<c03a4fc0>] (sh_eth_close+0x6c/0xa4)
      	[<c03a4fc0>] (sh_eth_close) from [<c0483234>] (__dev_close_many+0xac/0xd0)
      
      To fix this, clear phy_device.phy_num_led_triggers in the error path of
      phy_led_triggers_register() fails.
      
      Note that the "No phy led trigger registered for speed" message will
      still be printed on link speed changes, which is a good cue that
      something went wrong with the LED triggers.
      
      Fixes: 2e0bc452 ("net: phy: leds: add support for led triggers on phy link state change")
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      8a87fca8
  2. Jan 24, 2017
  3. Jan 23, 2017
  4. Jan 18, 2017
  5. Jan 17, 2017
  6. Jan 16, 2017
  7. Jan 11, 2017
    • Russell King's avatar
      net: phy: marvell: fix Marvell 88E1512 used in SGMII mode · a13c0652
      Russell King authored
      
      When an Marvell 88E1512 PHY is connected to a nic in SGMII mode, the
      fiber page is used for the SGMII host-side connection.  The PHY driver
      notices that SUPPORTED_FIBRE is set, so it tries reading the fiber page
      for the link status, and ends up reading the MAC-side status instead of
      the outgoing (copper) link.  This leads to incorrect results reported
      via ethtool.
      
      If the PHY is connected via SGMII to the host, ignore the fiber page.
      However, continue to allow the existing power management code to
      suspend and resume the fiber page.
      
      Fixes: 6cfb3bcc ("Marvell phy: check link status in case of fiber link.")
      Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      a13c0652
  8. Jan 09, 2017
    • Jean Delvare's avatar
      net: phy: Add Meson GXL PHY hardware dependency · 2ebae8bd
      Jean Delvare authored
      
      As I understand it the Meson GXL PHY driver is only useful on one
      architecture so only make it visible on that architecture.
      
      Signed-off-by: default avatarJean Delvare <jdelvare@suse.de>
      Fixes: 7334b3e4 ("net: phy: Add Meson GXL Internal PHY driver")
      Cc: Neil Armstrong <narmstrong@baylibre.com>
      Cc: Florian Fainelli <f.fainelli@gmail.com>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Cc: David S. Miller <davem@davemloft.net>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      2ebae8bd
    • Zefir Kurtisi's avatar
      phy state machine: failsafe leave invalid RUNNING state · 811a9191
      Zefir Kurtisi authored
      
      While in RUNNING state, phy_state_machine() checks for link changes by
      comparing phydev->link before and after calling phy_read_status().
      This works as long as it is guaranteed that phydev->link is never
      changed outside the phy_state_machine().
      
      If in some setups this happens, it causes the state machine to miss
      a link loss and remain RUNNING despite phydev->link being 0.
      
      This has been observed running a dsa setup with a process continuously
      polling the link states over ethtool each second (SNMPD RFC-1213
      agent). Disconnecting the link on a phy followed by a ETHTOOL_GSET
      causes dsa_slave_get_settings() / dsa_slave_get_link_ksettings() to
      call phy_read_status() and with that modify the link status - and
      with that bricking the phy state machine.
      
      This patch adds a fail-safe check while in RUNNING, which causes to
      move to CHANGELINK when the link is gone and we are still RUNNING.
      
      Signed-off-by: default avatarZefir Kurtisi <zefir.kurtisi@neratec.com>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      811a9191
  9. Jan 06, 2017
    • Grygorii Strashko's avatar
      net: phy: dp83867: fix irq generation · 5ca7d1ca
      Grygorii Strashko authored
      
      For proper IRQ generation by DP83867 phy the INT/PWDN pin has to be
      programmed as an interrupt output instead of a Powerdown input in
      Configuration Register 3 (CFG3), Address 0x001E, bit 7 INT_OE = 1. The
      current driver doesn't do this and as result IRQs will not be generated by
      DP83867 phy even if they are properly configured in DT.
      
      Hence, fix IRQ generation by properly configuring CFG3.INT_OE bit and
      ensure that Link Status Change (LINK_STATUS_CHNG_INT) and Auto-Negotiation
      Complete (AUTONEG_COMP_INT) interrupt are enabled. After this the DP83867
      driver will work properly in interrupt enabled mode.
      
      Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5ca7d1ca
  10. Dec 24, 2016
  11. Dec 20, 2016
  12. Dec 11, 2016
    • Timur Tabi's avatar
      net: phy: phy drivers should not set SUPPORTED_[Asym_]Pause · 529ed127
      Timur Tabi authored
      
      Instead of having individual PHY drivers set the SUPPORTED_Pause and
      SUPPORTED_Asym_Pause flags, phylib itself should set those flags,
      unless there is a hardware erratum or other special case.  During
      autonegotiation, the PHYs will determine whether to enable pause
      frame support.
      
      Pause frames are a feature that is supported by the MAC.  It is the MAC
      that generates the frames and that processes them.  The PHY can only be
      configured to allow them to pass through.
      
      This commit also effectively reverts the recently applied c7a61319
      ("net: phy: dp83848: Support ethernet pause frames").
      
      So the new process is:
      
      1) Unless the PHY driver overrides it, phylib sets the SUPPORTED_Pause
      and SUPPORTED_AsymPause bits in phydev->supported.  This indicates that
      the PHY supports pause frames.
      
      2) The MAC driver checks phydev->supported before it calls phy_start().
      If (SUPPORTED_Pause | SUPPORTED_AsymPause) is set, then the MAC driver
      sets those bits in phydev->advertising, if it wants to enable pause
      frame support.
      
      3) When the link state changes, the MAC driver checks phydev->pause and
      phydev->asym_pause,  If the bits are set, then it enables the corresponding
      features in the MAC.  The algorithm is:
      
      	if (phydev->pause)
      		The MAC should be programmed to receive and honor
                      pause frames it receives, i.e. enable receive flow control.
      
      	if (phydev->pause != phydev->asym_pause)
      		The MAC should be programmed to transmit pause
      		frames when needed, i.e. enable transmit flow control.
      
      Signed-off-by: default avatarTimur Tabi <timur@codeaurora.org>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      529ed127
  13. Dec 08, 2016
    • Woojung.Huh@microchip.com's avatar
      phy: add phy fixup unregister functions · f38e7a32
      Woojung.Huh@microchip.com authored
      
      >From : Woojung Huh <woojung.huh@microchip.com>
      
      Add functions to unregister phy fixup for modules.
      
      int phy_unregister_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask)
      	Unregister phy fixup from phy_fixup_list per bus_id, phy_uid &
      	phy_uid_mask
      
      int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask)
      	Unregister phy fixup from phy_fixup_list.
      	Use it for fixup registered by phy_register_fixup_for_uid()
      
      int phy_unregister_fixup_for_id(const char *bus_id)
      	Unregister phy fixup from phy_fixup_list.
      	Use it for fixup registered by phy_register_fixup_for_id()
      
      Signed-off-by: default avatarWoojung Huh <woojung.huh@microchip.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      f38e7a32
  14. Dec 07, 2016
  15. Dec 05, 2016
  16. Dec 02, 2016
  17. Dec 01, 2016
  18. Nov 30, 2016
  19. Nov 28, 2016
    • Martin Blumenstingl's avatar
      net: phy: realtek: fix enabling of the TX-delay for RTL8211F · e3230494
      Martin Blumenstingl authored
      
      The old logic always enabled the TX-delay when the phy-mode was set to
      PHY_INTERFACE_MODE_RGMII. There are dedicated phy-modes which tell the
      PHY driver to enable the RX and/or TX delays:
      - PHY_INTERFACE_MODE_RGMII should disable the RX and TX delay in the
        PHY (if required, the MAC should add the delays in this case)
      - PHY_INTERFACE_MODE_RGMII_ID should enable RX and TX delay in the PHY
      - PHY_INTERFACE_MODE_RGMII_TXID should enable the TX delay in the PHY
      - PHY_INTERFACE_MODE_RGMII_RXID should enable the RX delay in the PHY
        (currently not supported by RTL8211F)
      
      With this patch we enable the TX delay for PHY_INTERFACE_MODE_RGMII_ID
      and PHY_INTERFACE_MODE_RGMII_TXID.
      Additionally we now explicity disable the TX-delay, which seems to be
      enabled automatically after a hard-reset of the PHY (by triggering it's
      reset pin) to get a consistent state (as defined by the phy-mode).
      
      This fixes a compatibility problem with some SoCs where the TX-delay was
      also added by the MAC. With the TX-delay being applied twice the TX
      clock was off and TX traffic was broken or very slow (<10Mbit/s) on
      1000Mbit/s links.
      
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      e3230494
  20. Nov 26, 2016
  21. Nov 24, 2016
  22. Nov 18, 2016
  23. Nov 17, 2016
  24. Nov 16, 2016
  25. Nov 15, 2016
  26. Nov 14, 2016
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