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Commit 71ff8334 authored by Martin Oemus's avatar Martin Oemus
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uboot:dts: add pull-up for SAI1_TXD1 and tidy up other boot pin configs

parent 0da7c2ef
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1 merge request!126add generic platform and baseboard revision detection
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......@@ -41,12 +41,17 @@
imx8mm-evk {
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x80000000
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x00000016 // Fast Boot button on PConXs
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00000019 // ???
MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x00000146 // PFID detection pin for SOMs, pull-up required
MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x80000000 // Tanaro Fast Boot button, no special config required (?)
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x00000016 // Fast Boot button on PConXs (no special config required)
MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x00000016 // DEBUG_CABLE in pbb, No Pulldown, has external pulldown on pbb
MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00000156 // SW bootselect on PBB, requires pull up
MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x00000016 // DEBUG_CABLE in pbb, No Pulldown, has external pulldown on pbb
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x00000116 // UART1_TXEN on PBB, Pulldown to keep RS485 disabled on pbb during boot
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x00000116 // UART1_TXEN on PBB, Pulldown to keep RS485 disabled on pbb during boot
>;
};
......
......@@ -25,9 +25,15 @@
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x00000016 // DEBUG_CABLE on pbb for Plus, No Pulldown, has external pulldown on pbb
MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x00000156 // SW bootselect on PBB, requires pull up
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x00000116 // UART1_TXEN on PBB, Pulldown to keep RS485 disabled on pbb during boot
MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x00000146 // PFID detection pin for SOMs, pull-up required
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x00000016 // Fast Boot button on PConXs (no special config required)
MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x00000146 // SW bootselect on DualEspresso, requires pull up
MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x00000016 // DEBUG_CABLE on pbb for Plus, No Pulldown, has external pulldown on pbb
MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x00000156 // SW bootselect on PBB, requires pull up
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x00000116 // UART1_TXEN on PBB, Pulldown to keep RS485 disabled on pbb during boot
>;
};
......@@ -228,14 +234,6 @@
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
pinctrl_bootselect: bootselectgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x00000146
MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x00000106
MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x00000106
>;
};
};
&i2c1 {
......@@ -469,8 +467,3 @@
status = "okay";
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bootselect>;
};
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