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  1. Feb 20, 2015
  2. Feb 19, 2015
    • Keith Busch's avatar
      NVMe: Fix potential corruption on sync commands · 0c0f9b95
      Keith Busch authored
      
      This makes all sync commands uninterruptible and schedules without timeout
      so the controller either has to post a completion or the timeout recovery
      fails the command. This fixes potential memory or data corruption from
      a command timing out too early or woken by a signal. Previously any DMA
      buffers mapped for that command would have been released even though we
      don't know what the controller is planning to do with those addresses.
      
      Signed-off-by: default avatarKeith Busch <keith.busch@intel.com>
      0c0f9b95
    • Keith Busch's avatar
      NVMe: Remove unused variables · 48328518
      Keith Busch authored
      
      We don't track queues in a llist, subscribe to hot-cpu notifications,
      or internally retry commands. Delete the unused artifacts.
      
      Signed-off-by: default avatarKeith Busch <keith.busch@intel.com>
      48328518
    • Keith Busch's avatar
      NVMe: Fix scsi mode select llbaa setting · 9ac16938
      Keith Busch authored
      
      It should be a logical bitwise AND, not conditional.
      
      Signed-off-by: default avatarKeith Busch <keith.busch@intel.com>
      9ac16938
    • Keith Busch's avatar
      NVMe: Fix potential corruption during shutdown · 07836e65
      Keith Busch authored
      
      The driver has to end unreturned commands at some point even if the
      controller has not provided a completion. The driver tried to be safe by
      deleting IO queues prior to ending all unreturned commands. That should
      cause the controller to internally abort inflight commands, but IO queue
      deletion request does not have to be successful, so all bets are off. We
      still have to make progress, so to be extra safe, this patch doesn't
      clear a queue to release the dma mapping for a command until after the
      pci device has been disabled.
      
      This patch removes the special handling during device initialization
      so controller recovery can be done all the time. This is possible since
      initialization is not inlined with pci probe anymore.
      
      Reported-by: default avatarNilish Choudhury <nilesh.choudhury@oracle.com>
      Signed-off-by: default avatarKeith Busch <keith.busch@intel.com>
      07836e65
    • Keith Busch's avatar
      NVMe: Asynchronous controller probe · 2e1d8448
      Keith Busch authored
      
      This performs the longest parts of nvme device probe in scheduled work.
      This speeds up probe significantly when multiple devices are in use.
      
      Signed-off-by: default avatarKeith Busch <keith.busch@intel.com>
      2e1d8448
    • Keith Busch's avatar
      NVMe: Register management handle under nvme class · b3fffdef
      Keith Busch authored
      
      This creates a new class type for nvme devices to register their
      management character devices with. This is so we do not rely on miscdev
      to provide enough minors for as many nvme devices some people plan to
      use. The previous limit was approximately 60 NVMe controllers, depending
      on the platform and kernel. Now the limit is 1M, which ought to be enough
      for anybody.
      
      Since we have a new device class, it makes sense to attach the block
      devices under this as well, so part of this patch moves the management
      handle initialization prior to the namespaces discovery.
      
      Signed-off-by: default avatarKeith Busch <keith.busch@intel.com>
      b3fffdef
    • Keith Busch's avatar
      NVMe: Update SCSI Inquiry VPD 83h translation · 4f1982b4
      Keith Busch authored
      
      The original translation created collisions on Inquiry VPD 83 for many
      existing devices. Newer specifications provide other ways to translate
      based on the device's version can be used to create unique identifiers.
      
      Version 1.1 provides an EUI64 field that uniquely identifies each
      namespace, and 1.2 added the longer NGUID field for the same reason.
      Both follow the IEEE EUI format and readily translate to the SCSI device
      identification EUI designator type 2h. For devices implementing either,
      the translation will use this type, defaulting to the EUI64 8-byte type if
      implemented then NGUID's 16 byte version if not. If neither are provided,
      the 1.0 translation is used, and is updated to use the SCSI String format
      to guarantee a unique identifier.
      
      Knowing when to use the new fields depends on the nvme controller's
      revision. The NVME_VS macro was not decoding this correctly, so that is
      fixed in this patch and moved to a more appropriate place.
      
      Since the Identify Namespace structure required an update for the NGUID
      field, this patch adds the remaining new 1.2 fields to the structure.
      
      Signed-off-by: default avatarKeith Busch <keith.busch@intel.com>
      4f1982b4
    • Keith Busch's avatar
      NVMe: Metadata format support · e1e5e564
      Keith Busch authored
      
      Adds support for NVMe metadata formats and exposes block devices for
      all namespaces regardless of their format. Namespace formats that are
      unusable will have disk capacity set to 0, but a handle to the block
      device is created to simplify device management. A namespace is not
      usable when the format requires host interleave block and metadata in
      single buffer, has no provisioned storage, or has better data but failed
      to register with blk integrity.
      
      The namespace has to be scanned in two phases to support separate
      metadata formats. The first establishes the sector size and capacity
      prior to invoking add_disk. If metadata is required, the capacity will
      be temporarilly set to 0 until it can be revalidated and registered with
      the integrity extenstions after add_disk completes.
      
      The driver relies on the integrity extensions to provide the metadata
      buffer. NVMe requires this be a single physically contiguous region,
      so only one integrity segment is allowed per command. If the metadata
      is used for T10 PI, the driver provides mappings to save and restore
      the reftag physical block translation. The driver provides no-op
      functions for generate and verify if metadata is not used for protection
      information. This way the setup is always provided by the block layer.
      
      If a request does not supply a required metadata buffer, the command
      is failed with bad address. This could only happen if a user manually
      disables verify/generate on such a disk. The only exception to where
      this is okay is if the controller is capable of stripping/generating
      the metadata, which is possible on some types of formats.
      
      The metadata scatter gather list now occupies the spot in the nvme_iod
      that used to be used to link retryable IOD's, but we don't do that
      anymore, so the field was unused.
      
      Signed-off-by: default avatarKeith Busch <keith.busch@intel.com>
      e1e5e564
    • Preeti U Murthy's avatar
      cpuidle: powernv: Avoid endianness conversions while parsing DT · 70734a78
      Preeti U Murthy authored
      
      We currently read the information about idle states from the DT
      so as to populate the cpuidle table. Use those APIs to read from
      the DT that can avoid endianness conversions of the property values
      in the cpuidle driver.
      
      Signed-off-by: default avatarPreeti U Murthy <preeti@linux.vnet.ibm.com>
      Acked-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
      70734a78
    • Wolfram Sang's avatar
      i2c: designware-baytrail: another fixup for proper Kconfig dependencies · b4ad0510
      Wolfram Sang authored
      
      IOSF_MBI is tristate. Baytrail driver isn't.
      
      Reported-by: default avatarRandy Dunlap <rdunlap@infradead.org>
      Acked-by: default avatarDavid E. Box <david.e.box@linux.intel.com>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      b4ad0510
    • Christoph Hellwig's avatar
      rbd: convert to blk-mq · 7ad18afa
      Christoph Hellwig authored
      
      This converts the rbd driver to use the blk-mq infrastructure.  Except
      for switching to a per-request work item this is almost mechanical.
      
      This was tested by Alexandre DERUMIER in November, and found to give
      him 120000 iops, although the only comparism available was an old
      3.10 kernel which gave 80000iops.
      
      Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
      Reviewed-by: default avatarAlex Elder <elder@linaro.org>
      [idryomov@gmail.com: context, blk_mq_init_queue() EH]
      Signed-off-by: default avatarIlya Dryomov <idryomov@gmail.com>
      7ad18afa
    • Ilya Dryomov's avatar
      rbd: do not treat standalone as flatten · cf32bd9c
      Ilya Dryomov authored
      
      If the clone is resized down to 0, it becomes standalone.  If such
      resize is carried over while an image is mapped we would detect this
      and call rbd_dev_parent_put() which means "let go of all parent state,
      including the spec(s) of parent images(s)".  This leads to a mismatch
      between "rbd info" and sysfs parent fields, so a fix is in order.
      
          # rbd create --image-format 2 --size 1 foo
          # rbd snap create foo@snap
          # rbd snap protect foo@snap
          # rbd clone foo@snap bar
          # DEV=$(rbd map bar)
          # rbd resize --allow-shrink --size 0 bar
          # rbd resize --size 1 bar
          # rbd info bar | grep parent
                  parent: rbd/foo@snap
      
      Before:
      
          # cat /sys/bus/rbd/devices/0/parent
          (no parent image)
      
      After:
      
          # cat /sys/bus/rbd/devices/0/parent
          pool_id 0
          pool_name rbd
          image_id 10056b8b4567
          image_name foo
          snap_id 2
          snap_name snap
          overlap 0
      
      Signed-off-by: default avatarIlya Dryomov <idryomov@redhat.com>
      Reviewed-by: default avatarJosh Durgin <jdurgin@redhat.com>
      Reviewed-by: default avatarAlex Elder <elder@linaro.org>
      cf32bd9c
    • Ilya Dryomov's avatar
      rbd: fix error paths in rbd_dev_refresh() · 73e39e4d
      Ilya Dryomov authored
      
      header_rwsem should be released on errors.  Also remove useless
      rbd_dev->mapping.size != rbd_dev->header.image_size test.
      
      Signed-off-by: default avatarIlya Dryomov <idryomov@redhat.com>
      73e39e4d
    • Rickard Strandqvist's avatar
      rbd: nuke copy_token() · 3a25cf43
      Rickard Strandqvist authored
      
      It's been largely superseded by dup_token() and unused for over
      2 years, identified by cppcheck.
      
      Signed-off-by: default avatarRickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
      [idryomov@redhat.com: changelog]
      Signed-off-by: default avatarIlya Dryomov <idryomov@redhat.com>
      3a25cf43
    • Arnd Bergmann's avatar
      cpufreq: s3c: remove last use of resume_clocks callback · 67fadaa2
      Arnd Bergmann authored
      
      Commit 32726d2d ("ARM: SAMSUNG: Remove legacy clock code")
      already removed the callback pointer, but there was one remaining
      user:
      
      drivers/cpufreq/s3c24xx-cpufreq.c: In function 's3c_cpufreq_resume_clocks':
      drivers/cpufreq/s3c24xx-cpufreq.c:149:14: error: 'struct s3c_cpufreq_info' has no member named 'resume_clocks'
        cpu_cur.info->resume_clocks();
                    ^
      
      Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      Fixes: 32726d2d ("ARM: SAMSUNG: Remove legacy clock code")
      Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
      Cc: 3.17+ <stable@vger.kernel.org> # v3.17+
      Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
      67fadaa2
    • Arnd Bergmann's avatar
      cpufreq: s3c: remove incorrect __init annotations · 61882b63
      Arnd Bergmann authored
      
      The two functions s3c2416_cpufreq_driver_init and s3c_cpufreq_register
      are marked init but are called from a context that might be run after
      the __init sections are discarded, as the compiler points out:
      
      WARNING: vmlinux.o(.data+0x1ad9dc): Section mismatch in reference from the variable s3c2416_cpufreq_driver to the function .init.text:s3c2416_cpufreq_driver_init()
      WARNING: drivers/built-in.o(.text+0x35b5dc): Section mismatch in reference from the function s3c2410a_cpufreq_add() to the function .init.text:s3c_cpufreq_register()
      
      This removes the __init markings.
      
      Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
      Cc: All applicable <stable@vger.kernel.org>
      Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
      61882b63
  3. Feb 18, 2015
    • Bryan O'Donoghue's avatar
      x86/intel/quark: Add Isolated Memory Regions for Quark X1000 · 28a375df
      Bryan O'Donoghue authored
      
      Intel's Quark X1000 SoC contains a set of registers called
      Isolated Memory Regions. IMRs are accessed over the IOSF mailbox
      interface. IMRs are areas carved out of memory that define
      read/write access rights to the various system agents within the
      Quark system. For a given agent in the system it is possible to
      specify if that agent may read or write an area of memory
      defined by an IMR with a granularity of 1 KiB.
      
      Quark_SecureBootPRM_330234_001.pdf section 4.5 details the
      concept of IMRs quark-x1000-datasheet.pdf section 12.7.4 details
      the implementation of IMRs in silicon.
      
      eSRAM flush, CPU Snoop write-only, CPU SMM Mode, CPU non-SMM
      mode, RMU and PCIe Virtual Channels (VC0 and VC1) can have
      individual read/write access masks applied to them for a given
      memory region in Quark X1000. This enables IMRs to treat each
      memory transaction type listed above on an individual basis and
      to filter appropriately based on the IMR access mask for the
      memory region. Quark supports eight IMRs.
      
      Since all of the DMA capable SoC components in the X1000 are
      mapped to VC0 it is possible to define sections of memory as
      invalid for DMA write operations originating from Ethernet, USB,
      SD and any other DMA capable south-cluster component on VC0.
      Similarly it is possible to mark kernel memory as non-SMM mode
      read/write only or to mark BIOS runtime memory as SMM mode
      accessible only depending on the particular memory footprint on
      a given system.
      
      On an IMR violation Quark SoC X1000 systems are configured to
      reset the system, so ensuring that the IMR memory map is
      consistent with the EFI provided memory map is critical to
      ensure no IMR violations reset the system.
      
      The API for accessing IMRs is based on MTRR code but doesn't
      provide a /proc or /sys interface to manipulate IMRs. Defining
      the size and extent of IMRs is exclusively the domain of
      in-kernel code.
      
      Quark firmware sets up a series of locked IMRs around pieces of
      memory that firmware owns such as ACPI runtime data. During boot
      a series of unlocked IMRs are placed around items in memory to
      guarantee no DMA modification of those items can take place.
      Grub also places an unlocked IMR around the kernel boot params
      data structure and compressed kernel image. It is necessary for
      the kernel to tear down all unlocked IMRs in order to ensure
      that the kernel's view of memory passed via the EFI memory map
      is consistent with the IMR memory map. Without tearing down all
      unlocked IMRs on boot transitory IMRs such as those used to
      protect the compressed kernel image will cause IMR violations and system reboots.
      
      The IMR init code tears down all unlocked IMRs and sets a
      protective IMR around the kernel .text and .rodata as one
      contiguous block. This sanitizes the IMR memory map with respect
      to the EFI memory map and protects the read-only portions of the
      kernel from unwarranted DMA access.
      
      Tested-by: default avatarOng, Boon Leong <boon.leong.ong@intel.com>
      Signed-off-by: default avatarBryan O'Donoghue <pure.logic@nexus-software.ie>
      Reviewed-by: default avatarAndy Shevchenko <andy.schevchenko@gmail.com>
      Reviewed-by: default avatarDarren Hart <dvhart@linux.intel.com>
      Reviewed-by: default avatarOng, Boon Leong <boon.leong.ong@intel.com>
      Cc: andy.shevchenko@gmail.com
      Cc: dvhart@infradead.org
      Link: http://lkml.kernel.org/r/1422635379-12476-2-git-send-email-pure.logic@nexus-software.ie
      
      
      Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
      28a375df
    • Stefan Wahren's avatar
      Revert "clk: mxs: Fix invalid 32-bit access to frac registers" · a9261487
      Stefan Wahren authored
      
      Revert commit 039e5970 (clk: mxs: Fix invalid 32-bit access to frac
      registers), because it leads to a faulty spi communication on mx28evk.
      
      Signed-off-by: default avatarStefan Wahren <stefan.wahren@i2se.com>
      Reported-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
      Tested-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
      a9261487
    • Emil Medve's avatar
      clk: qoriq: Add support for the platform PLL · a513b72c
      Emil Medve authored
      
      Change-Id: Iac11ed95f274485a86d2c11f32a3dc502bcd020f
      Signed-off-by: default avatarEmil Medve <Emilian.Medve@Freescale.com>
      Acked-by: default avatarTang Yuantian <Yuantian.Tang@freescale.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
      a513b72c
    • Mika Westerberg's avatar
      ACPI / LPSS: Deassert resets for SPI host controllers on Braswell · 3095794a
      Mika Westerberg authored
      
      On some Braswell systems BIOS leaves resets for SPI host controllers
      active. This prevents the SPI driver from transferring messages on wire.
      
      Fix this in similar way that we do for I2C already by deasserting resets
      for the SPI host controllers.
      
      Reported-by: default avatarYang A Fang <yang.a.fang@intel.com>
      Signed-off-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
      Cc: 3.17+ <stable@vger.kernel.org> # 3.17+
      Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
      3095794a
    • Mika Westerberg's avatar
      ACPI / LPSS: Always disable I2C host controllers · 3293c7b8
      Mika Westerberg authored
      
      On Baytrail and Braswell the BIOS might leave the I2C host controllers
      enabled, probably because it uses them for its own purposes. This is fine
      in normal cases because the I2C driver will disable the hardware when it
      is probed anyway.
      
      However, in case of suspend to disk it is different story. If the driver
      happens to be compiled as a module the boot kernel never loads the driver
      thus leaving host controllers enabled upon loading the hibernation image.
      
      The I2C host controller interrupt mask register has default value of 0x8ff,
      in other words it has most of the interrupts unmasked. When combined with
      the fact that the host controller is enabled, the driver immediately starts
      getting interrupts even before its resume hook is called (once IO-APIC is
      resumed). Since the driver is not prepared for this it will crash the
      kernel due to NULL pointer derefence because dev->msgs is NULL.
      
      Unfortunately we were not able to get full backtrace to from the console
      which could be reproduced here.
      
      In order to fix this even when the driver is compiled as module, we disable
      the I2C host controllers in byt_i2c_setup() before devices are created.
      
      Reported-by: default avatarYu Chen <yu.c.chen@intel.com>
      Signed-off-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
      Cc: 3.17+ <stable@vger.kernel.org> # 3.17+
      Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
      3293c7b8
    • Javier Martinez Canillas's avatar
      clk: Replace explicit clk assignment with __clk_hw_set_clk · 4e907ef6
      Javier Martinez Canillas authored
      
      The change in the clk API to return a per-user clock instance, moved
      the clock state to struct clk_core so now the struct clk_hw .core field
      is used instead of .clk for most operations.
      
      So for hardware clocks that needs to share the same clock state, both
      the .core and .clk pointers have to be assigned but currently only the
      .clk is set. This leads to NULL pointer dereference when the operations
      try to access the hw clock .core. For example, the composite clock rate
      and mux components didn't have a .core set which leads to this error:
      
      Unable to handle kernel NULL pointer dereference at virtual address 00000034
      pgd = c0004000
      [00000034] *pgd=00000000
      Internal error: Oops: 5 [#1] PREEMPT SMP ARM
      Modules linked in:
      CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.19.0-next-20150211-00002-g1fb7f0e1150d #423
      Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
      task: ee480000 ti: ee488000 task.ti: ee488000
      PC is at clk_mux_determine_rate_flags+0x14/0x19c
      LR is at __clk_mux_determine_rate+0x24/0x2c
      pc : [<c03a355c>]    lr : [<c03a3734>]    psr: a0000113
      sp : ee489ce8  ip : ee489d84  fp : ee489d84
      r10: 0000005c  r9 : 00000001  r8 : 016e3600
      r7 : 00000000  r6 : 00000000  r5 : ee442200  r4 : ee440c98
      r3 : ffffffff  r2 : 00000000  r1 : 016e3600  r0 : ee440c98
      Flags: NzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
      Control: 10c5387d  Table: 4000406a  DAC: 00000015
      Process swapper/0 (pid: 1, stack limit = 0xee488210)
      Stack: (0xee489ce8 to 0xee48a000)
      9ce0:                   00000000 ffffffff 60000113 ee440c98 ee442200 00000000
      9d00: 016e3600 ffffffff 00000001 0000005c ee489d84 c03a3734 ee489d80 ee489d84
      9d20: 00000000 c048b130 00000400 c03a5798 ee489d80 ee489d84 c0607f60 ffffffea
      9d40: 00000001 00000001 ee489d5c c003f844 c06e3340 ee402680 ee440d0c ed935000
      9d60: 016e3600 00000003 00000001 0000005c eded3700 c03a11a0 ee489d80 ee489d84
      9d80: 016e3600 ee402680 c05b413a eddc9900 016e3600 c03a1228 00000000 ffffffff
      9da0: ffffffff eddc9900 016e3600 c03a1c1c ffffffff 016e3600 ed8c6710 c03d6ce4
      9dc0: eded3400 00000000 00000000 c03c797c 00000001 0000005c eded3700 eded3700
      9de0: 000005e0 00000001 0000005c c03db8ac c06e7e54 c03c8f08 00000000 c06e7e64
      9e00: c06b6e74 c06e7f64 000005e0 c06e7df8 c06e5100 00000000 c06e7e6c c06e7f54
      9e20: 00000000 00000000 eebd9550 00000000 c06e7da0 c06e7e54 ee7b5010 c06e7da0
      9e40: eddc9690 c06e7db4 c06b6e74 00000097 00000000 c03d4398 00000000 ee7b5010
      9e60: eebd9550 c06e7da0 00000000 c03db824 ee7b5010 fffffffe c06e7db4 c0299c7c
      9e80: ee7b5010 c072a05c 00000000 c0298858 ee7b5010 c06e7db4 ee7b5044 00000000
      9ea0: eddc9580 c0298a04 c06e7db4 00000000 c0298978 c02971d4 ee405c78 ee732b40
      9ec0: c06e7db4 eded3800 c06d6738 c0298044 c0608300 c06e7db4 00000000 c06e7db4
      9ee0: 00000000 c06beb58 c06beb58 c0299024 00000000 c068dd00 00000000 c0008944
      9f00: 00000038 c049013c ee462200 c0711920 ee480000 60000113 c06c2cb0 00000000
      9f20: 00000000 c06c2cb0 60000113 00000000 ef7fcafc 00000000 c0640194 c00389ec
      9f40: c05ec3a8 c063f824 00000006 00000006 c06c2c50 c0696444 00000006 c0696424
      9f60: c06ee1c0 c066b588 c06b6e74 00000097 00000000 c066bd44 00000006 00000006
      9f80: c066b588 c003d684 00000000 c0481938 00000000 00000000 00000000 00000000
      9fa0: 00000000 c0481940 00000000 c000e680 00000000 00000000 00000000 00000000
      9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
      9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
      [<c03a355c>] (clk_mux_determine_rate_flags) from [<c03a3734>] (__clk_mux_determine_rate+0x24/0x2c)
      [<c03a3734>] (__clk_mux_determine_rate) from [<c03a5798>] (clk_composite_determine_rate+0xbc/0x238)
      [<c03a5798>] (clk_composite_determine_rate) from [<c03a11a0>] (clk_core_round_rate_nolock+0x5c/0x9c)
      [<c03a11a0>] (clk_core_round_rate_nolock) from [<c03a1228>] (__clk_round_rate+0x38/0x40)
      [<c03a1228>] (__clk_round_rate) from [<c03a1c1c>] (clk_round_rate+0x20/0x38)
      [<c03a1c1c>] (clk_round_rate) from [<c03d6ce4>] (max98090_dai_set_sysclk+0x34/0x118)
      [<c03d6ce4>] (max98090_dai_set_sysclk) from [<c03c797c>] (snd_soc_dai_set_sysclk+0x38/0x80)
      [<c03c797c>] (snd_soc_dai_set_sysclk) from [<c03db8ac>] (snow_late_probe+0x24/0x48)
      [<c03db8ac>] (snow_late_probe) from [<c03c8f08>] (snd_soc_register_card+0xf04/0x1070)
      [<c03c8f08>] (snd_soc_register_card) from [<c03d4398>] (devm_snd_soc_register_card+0x30/0x64)
      [<c03d4398>] (devm_snd_soc_register_card) from [<c03db824>] (snow_probe+0x68/0xcc)
      [<c03db824>] (snow_probe) from [<c0299c7c>] (platform_drv_probe+0x48/0x98)
      [<c0299c7c>] (platform_drv_probe) from [<c0298858>] (driver_probe_device+0x114/0x234)
      [<c0298858>] (driver_probe_device) from [<c0298a04>] (__driver_attach+0x8c/0x90)
      [<c0298a04>] (__driver_attach) from [<c02971d4>] (bus_for_each_dev+0x54/0x88)
      [<c02971d4>] (bus_for_each_dev) from [<c0298044>] (bus_add_driver+0xd8/0x1cc)
      [<c0298044>] (bus_add_driver) from [<c0299024>] (driver_register+0x78/0xf4)
      [<c0299024>] (driver_register) from [<c0008944>] (do_one_initcall+0x80/0x1d0)
      [<c0008944>] (do_one_initcall) from [<c066bd44>] (kernel_init_freeable+0x10c/0x1d8)
      [<c066bd44>] (kernel_init_freeable) from [<c0481940>] (kernel_init+0x8/0xe4)
      [<c0481940>] (kernel_init) from [<c000e680>] (ret_from_fork+0x14/0x34)
      Code: e24dd00c e5907000 e1a08001 e88d000c (e5970034)
      
      The changes were made using the following cocinelle semantic patch:
      
      @i@
      @@
      
      @depends on i@
      identifier dst;
      @@
      
      - dst->clk = hw->clk;
      + __clk_hw_set_clk(dst, hw);
      
      @depends on i@
      identifier dst;
      @@
      
      - dst->hw.clk = hw->clk;
      + __clk_hw_set_clk(&dst->hw, hw);
      
      Fixes: 035a61c3 ("clk: Make clk API return per-user struct clk instances")
      Signed-off-by: default avatarJavier Martinez Canillas <javier.martinez@collabora.co.uk>
      Reviewed-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
      4e907ef6
    • Javier Martinez Canillas's avatar
      clk: Don't dereference parent clock if is NULL · 9e0ad7d2
      Javier Martinez Canillas authored
      
      The clock passed as an argument to clk_mux_determine_rate_flags()
      has the CLK_SET_RATE_PARENT flag set but it has no parent, then a
      NULL pointer will tried to be dereferenced.
      
      This shouldn't happen since setting that flag for a clock with no
      parent is a bug but the core should be robust to handle that case.
      
      Fixes: 035a61c3 ("clk: Make clk API return per-user struct clk instances")
      Signed-off-by: default avatarJavier Martinez Canillas <javier.martinez@collabora.co.uk>
      Reviewed-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
      9e0ad7d2
    • Haggai Eran's avatar
      IB/mlx5: Enable the ODP capability query verb · 1707cb4a
      Haggai Eran authored
      
      Re-enable the on-demand paging capability query through the
      extended query device verb.
      
      Signed-off-by: default avatarHaggai Eran <haggaie@mellanox.com>
      Reviewed-by: default avatarYann Droneaud <ydroneaud@opteya.com>
      Signed-off-by: default avatarRoland Dreier <roland@purestorage.com>
      1707cb4a
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