- Jul 23, 2012
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Thomas Langer authored
The external bus unit (EBU) found on the FALCON SoC has spi emulation that is designed for serial flash access. This driver has only been tested with m25p80 type chips. The hardware has no support for other types of spi peripherals. Signed-off-by:
Thomas Langer <thomas.langer@lantiq.com> Signed-off-by:
John Crispin <blogic@openwrt.org> Cc: spi-devel-general@lists.sourceforge.net Cc: linux-mips@linux-mips.org Acked-by:
Grant Likely <grant.likely@secretlab.ca> Patchwork: https://patchwork.linux-mips.org/patch/3844/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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- Jul 20, 2012
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Lars-Peter Clausen authored
This patch adds support for the I2C-SPI bridge which can be found on the Analog Devices AD-FMCOMMS1-EBZ board. Signed-off-by:
Lars-Peter Clausen <lars@metafoo.de> Signed-off-by:
Mark Brown <broonie@opensource.wolfsonmicro.com>
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- Apr 27, 2012
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Scott Jiang authored
This controller is only for blackfin 5xx soc, so rename it to BFIN5XX Signed-off-by:
Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Mar 09, 2012
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Florian Fainelli authored
This patch adds support for the SPI controller found on the Broadcom BCM63xx SoCs. Signed-off-by:
Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> Signed-off-by:
Florian Fainelli <florian@openwrt.org> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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Zhiwu Song authored
CSR SiRFprimaII has two SPIs (SPI0 and SPI1). Features: * Master and slave modes * 8-/12-/16-/32-bit data unit * 256 bytes receive data FIFO and 256 bytes transmit data FIFO * Multi-unit frame * Configurable SPI_EN (chip select pin) active state * Configurable SPI_CLK polarity * Configurable SPI_CLK phase * Configurable MSB/LSB first Signed-off-by:
Zhiwu Song <zhiwu.song@csr.com> Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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Kuninori Morimoto authored
This patch adds SuperH HSPI driver. It is still prototype driver, but has enough function at this point. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Mar 08, 2012
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Shimoda, Yoshihiro authored
The SH7757 has RSPI module. This patch supports it. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Jul 04, 2011
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Peter Korsgaard authored
It was equivalent to spi-gpio, and there's no longer any in-tree users of it, so get rid of it. Signed-off-by:
Peter Korsgaard <jacmet@sunsite.dk> Acked-by:
Ben Dooks <ben-linux@fluff.org> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Jun 06, 2011
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Grant Likely authored
Sort the SPI makefile and enforce the naming convention spi_*.c for spi drivers. This change also rolls the contents of atmel_spi.h into the .c file since there is only one user of that particular include file. v2: - Use 'spi-' prefix instead of 'spi_' to match what seems to be be the predominant pattern for subsystem prefixes. - Clean up filenames in Kconfig and header comment blocks Signed-off-by:
Grant Likely <grant.likely@secretlab.ca> Acked-by:
Wolfram Sang <w.sang@pengutronix.de> Acked-by:
Linus Walleij <linus.walleij@linaro.org>
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- May 27, 2011
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Cliff Cai authored
The Blackfin SPORT peripheral is a pretty flexible device. With enough coaching, we can make it generate SPI compatible waveforms. This is desirable as the SPORT can run at much higher clock frequencies than the dedicated on-chip SPI peripheral, and it can do full duplex DMA. It also opens up the possibility of multiple SPI buses in case someone wants to dedicate a whole bus to a specific part that does not play well with others. Signed-off-by:
Cliff Cai <cliff.cai@analog.com> Signed-off-by:
Bryan Wu <cooloney@kernel.org> Signed-off-by:
Michael Hennerich <michael.hennerich@analog.com> Signed-off-by:
Mike Frysinger <vapier@gentoo.org> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Mar 15, 2011
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Cyril Chemparathy authored
This patch adds an SPI master implementation that operates on top of an underlying TI-SSP port. Acked-by:
Grant Likely <grant.likely@secretlab.ca> Signed-off-by:
Cyril Chemparathy <cyril@ti.com> Signed-off-by:
Sekhar Nori <nsekhar@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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- Feb 22, 2011
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Yoshihiro Shimoda authored
The SH7757 has SPI0 module. This patch supports it. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [grant.likely@secretlab.ca: fixed Makefile ordering, added __dev{init,exit} annotations, removed DRIVER_VERSION (this is mainline, the version == the kernel version) and tidied some indentation & style stuff] Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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Thomas Chou authored
This patch adds a new SPI driver to support the Altera SOPC Builder SPI component. It uses the bitbanging library. Signed-off-by:
Thomas Chou <thomas@wytron.com.tw> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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Thomas Chou authored
This patch adds support of OpenCores tiny SPI driver. http://opencores.org/project,tiny_spi Signed-off-by:
Thomas Chou <thomas@wytron.com.tw> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Jan 18, 2011
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Gabor Juhos authored
The Atheros AR71XX/AR724X/AR913X SoCs have a built-in SPI controller. This patch implements a driver for that. Signed-off-by:
Gabor Juhos <juhosg@openwrt.org> Cc: David Brownell <dbrownell@users.sourceforge.net> Cc: spi-devel-general@lists.sourceforge.net Acked-by:
Grant Likely <grant.likely@secretlab.ca> Cc: linux-mips@linux-mips.org Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1960/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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- Dec 24, 2010
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Feng Tang authored
dw_spi driver in upstream only supports PIO mode, and this patch will support it to cowork with the Designware dma controller used on Intel Moorestown platform, at the same time it provides a general framework to support dw_spi core to cowork with dma controllers on other platforms It has been tested with a Option GTM501L 3G modem and Infenion 60x60 modem. To use DMA mode, DMA controller 2 of Moorestown has to be enabled Also change the dma interface suggested by Linus Walleij. Acked-by:
Linus Walleij <linus.walleij@stericsson.com> Signed-off-by:
Feng Tang <feng.tang@intel.com> [Typo fix and renames to match intel_mid_dma renaming] Signed-off-by:
Vinod Koul <vinod.koul@intel.com> Signed-off-by:
Alan Cox <alan@linux.intel.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Dec 01, 2010
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Sebastian Andrzej Siewior authored
Sodaville's SPI controller is very much the same as in PXA25x. The difference: - The RX/TX FIFO is only 4 words deep instead of 16 - No DMA support - The SPI controller offers a CS functionality Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by:
Dirk Brandewie <dirk.brandewie@gmail.com>
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- Nov 10, 2010
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Grant Likely authored
Now that the of_platform_bus_type has been merged with the platform bus type, a single platform driver can handle both OF and non-OF use cases. This patch merges the OF support into the platform driver. Signed-off-by:
Grant Likely <grant.likely@secretlab.ca> Tested-by:
Michal Simek <monstr@monstr.eu>
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Grant Likely authored
This patch merges the platform driver support into the main body of xilinx_spi.c in preparation for merging the OF and non-OF support code. Signed-off-by:
Grant Likely <grant.likely@secretlab.ca> Tested-by:
Michal Simek <monstr@monstr.eu>
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- Oct 22, 2010
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Erik Gilling authored
v2 changes: from Thierry Reding: * add "select TEGRA_SYSTEM_DMA" to Kconfig from Grant Likely: * add oneline description to header * inline references to DRIVER_NAME * inline references to BUSY_TIMEOUT * open coded bytes_per_word() * spi_readl/writel -> spi_tegra_readl/writel * move transfer validation to spi_tegra_transfer * don't request_mem_region iomem as platform bus does that for us * __exit -> __devexit v3 changes: from Russell King: * put request_mem_region back int from Grant Likely: * remove #undef DEBUG * add SLINK_ to register bit defines * remove unused bytes_per_word * make spi_tegra_readl/writel static linine * various refactoring for clarity * mark err if BSY bit is not cleared after 1000 retries * move spinlock to protect setting of RDY bit * subsys_initcall -> module_init v3 changes: from Grant Likely: * update spi_tegra to use PTR_ERRless dma API v4 changes: from Grant Likely: * remove empty spi_tegra_cleanup fucntion * allow device ids of -1 Signed-off-by:
Erik Gilling <konkers@android.com> Acked-by:
Grant Likely <grant.likely@secretlab.ca> Cc: Thierry Reding <thierry.reding@avionic-design.de> Cc: Russell King <linux@arm.linux.org.uk> spi: tegra: cleanups from upstream review Change-Id: Icecf7e64efcb39de072a15234ba1faa4bad40d25 Signed-off-by:
Erik Gilling <konkers@android.com>
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- Oct 13, 2010
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Mingkai Hu authored
Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by:
Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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Mingkai Hu authored
Refactor the common code in file spi_fsl_spi.c to spi_fsl_lib.c used by SPI/eSPI controller driver as a library, and leave the QE/CPM SPI controller code in the SPI controller driver spi_fsl_spi.c. Because the register map of the SPI controller and eSPI controller is so different, also leave the code operated the register to the driver code, not the common code. Signed-off-by:
Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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Mingkai Hu authored
This will pave the way to refactor out the common code which can be used by the eSPI controller driver, and rename the SPI controller dirver to the file spi_fsl_spi.c. Signed-off-by:
Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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matt mooney authored
Replace EXTRA_CFLAGS with ccflags-y. Signed-off-by:
matt mooney <mfm@muteddisk.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Oct 08, 2010
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Masayuki Ohtake authored
Topcliff PCH is the platform controller hub that is going to be used in Intel's upcoming general embedded platform. All IO peripherals in Topcliff PCH are actually devices sitting on AMBA bus. This patch adds a driver for the SPI bus integrated into the Topcliff device. Signed-off-by:
Masayuki Ohtake <masa-korg@dsn.okisemi.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- May 25, 2010
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Anatolij Gustschin authored
Signed-off-by:
John Rigby <jcrigby@gmail.com> Signed-off-by:
Anatolij Gustschin <agust@denx.de> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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Mika Westerberg authored
This patch adds an SPI master driver for the Cirrus EP93xx SPI controller found in EP93xx chips. Signed-off-by:
Mika Westerberg <mika.westerberg@iki.fi> Signed-off-by:
H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by:
H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Jan 21, 2010
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Jean-Hugues Deschenes authored
Adds a memory-mapped I/O dw_spi platform device. Signed-off-by:
Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Jan 20, 2010
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Steven King authored
Add support for the QSPI controller found some on Freescale/Motorola Coldfire MCUs. Full duplex, active high cs, spi modes 0-3 and word sizes 8-16 bits are supported. The hardware drives the MISO, MOSI and SCLK lines, but the chip selects are managed via GPIO and must be configured by the board code. The QSPI controller has an 80 byte buffer which allows us to transfer up to 16 words at a time. For transfers longer than 16 words, we split the buffer in half so we can update in one half while the controller is operating on the other half. Interrupt latencies then ultimately limits our sustained thru-put to something less than half the maximum speed supported by the part. Signed-off-by:
Steven King <sfking@fdwdc.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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Sandeep Paulraj authored
This patch adds support for a SPI master driver for the DaVinci series of SOCs Signed-off-by:
Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by:
Mark A. Greer <mgreer@mvista.com> Signed-off-by:
Philby John <pjohn@in.mvista.com> Signed-off-by:
Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by:
Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Dec 17, 2009
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Jassi Brar authored
Each SPI controller has exactly one CS line and as such doesn't provide for multi-cs. We implement a workaround to support multi-cs by _not_ configuring the mux'ed CS pin for each SPI controller. The CS mechanism is assumed to be fully machine specific - the driver doesn't even assume some GPIO pin is used to control the CS. The driver selects between DMA and POLLING mode depending upon the xfer size - DMA mode for xfers bigger than FIFO size, POLLING mode otherwise. The driver has been designed to be capable of running SoCs since s3c64xx and till date, for that reason some of the register fields have been passed via, SoC specific, platform data. Signed-off-by:
Jassi Brar <jassi.brar@samsung.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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Ben Dooks authored
Add pseudo-DMA by FIQ to the S3C24XX SPI driver. This allows the driver to get DMA-like performance where there are either no free DMA channels or when doing transfers that required both TX and RX data paths. Since this patch requires the addition of an assembly file to hold the FIQ code, we rename the module (instead of adding a rename of the .c file to this patch). We expect most users are loading this via udev and thus there should be no change to the userland configuration. Signed-off-by:
Ben Dooks <ben@simtec.co.uk> Signed-off-by:
Simtec Linux Team <linux@simtec.co.uk> Cc: David Brownell <david-b@pacbell.net> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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Feng Tang authored
Driver for the Designware SPI core, it supports multipul interfaces like PCI/APB etc. User can use "dw_apb_ssi_db.pdf" from Synopsys as HW datasheet. [randy.dunlap@oracle.com: fix build] [akpm@linux-foundation.org: build fix] Signed-off-by:
Feng Tang <feng.tang@intel.com> Cc: David Brownell <david-b@pacbell.net> Signed-off-by:
Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Dec 13, 2009
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Cory Maccarrone authored
This change adds the OMAP SPI 100k driver created by Fabrice Crohas <fcrohas@gmail.com>. This SPI bus is found on OMAP7xx-series smartphones, and for many, the touchscreen is attached to this bus. The lion's share of the work was done by Fabrice on this driver -- I am merely porting it from the Linwizard project on his behalf. Signed-off-by:
Cory Maccarrone <darkstar6262@gmail.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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Wan ZongShun authored
Signed-off-by:
Wan ZongShun <mcuos.com@gmail.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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Magnus Damm authored
This patch is V2 of SPI Master support for the SuperH MSIOF. Full duplex, spi mode 0-3, active high cs, 3-wire and lsb first should all be supported, but the driver has so far only been tested with "mmc_spi". The MSIOF hardware comes with 32-bit FIFOs for receive and transmit, and this driver simply breaks the SPI messages into FIFO-sized chunks. The MSIOF hardware manages the pins for clock, receive and transmit (sck/miso/mosi), but the chip select pin is managed by software and must be configured as a regular GPIO pin by the board code. Performance wise there is still room for improvement, but on a Ecovec board with the built-in sh7724 MSIOF0 this driver gets Mini-sd read speeds of about half a megabyte per second. Future work include better clock setup and merging of 8-bit transfers into 32-bit words to reduce interrupt load and improve throughput. Signed-off-by:
Magnus Damm <damm@opensource.se> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Dec 09, 2009
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Richard Röjfors authored
This patch adds in a platform device driver using the xilinx_spi common module. Tested-by:
John Linn <John.Linn@xilinx.com> Signed-off-by:
Richard Röjfors <richard.rojfors@mocean-labs.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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Richard Röjfors authored
This patch splits the xilinx_spi driver into a generic part and a OF driver part. The reason for this is to later add in a platform driver as well. Tested-by:
John Linn <John.Linn@xilinx.com> Signed-off-by:
Richard Röjfors <richard.rojfors@mocean-labs.com> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Nov 04, 2009
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Grant Likely authored
Adds support for the dedicated SPI device on the Freescale MPC5200(b) SoC. Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- Oct 01, 2009
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Uwe Kleine-König authored
This makes the filename match the Kconfig symbol and the driver name. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: David Brownell <dbrownell@users.sourceforge.net> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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