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Integrate gitlab-ci/lpag/new_board_config and 19 more

GitBot requested to merge integrate/gitlab-ci/lpag/new_board_config/into/kirkstone into kirkstone

Commit: edgehog/infrastructure/gitlab-ci@e88df1a2

[BOARD][CONFIG] Insert config for TigerLake boards

  • Insert configuration file for boards based on Intel Tiger Lake boards

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Commit: edgehog/infrastructure/gitlab-ci@944f20d9

[NUM_MAX_CPU] Reduce the number of CPU threads

  • Set the number to 32 and increase number of parallel jobs for the runner

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Commit: edgehog/infrastructure/gitlab-ci@4a79ac2b

[TIMEOUT] Increase timeout on notify/changelog job

  • Increase the timeout to 4h because of increased overload on CI/CD pipeline

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Commit: edgehog/infrastructure/gitlab-ci@d710ecdb

[BOARD][CONFIG] Insert config for c72n board

  • Remove c61 config file since not released yet

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Commit: edgehog/infrastructure/gitlab-ci@bf698958

[928] Fix on 8x512M RAM configuration file

  • Fix on AZURE_PATH variable position

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Commit: edgehog/infrastructure/gitlab-ci@e2413972

[962] Add 962 i.MX6 board configuration file

  • The configuration file allows to build 3 different RAM configurations: 2x256M, 4x256M, 4x512M
  • Insert preliminary test integration job

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Commit: edgehog/infrastructure/gitlab-ci@6de4af63

[BOARD][CONFIG] Insert config for 928 board

  • Add configuration file for 928 considering all the supported RAM configurations
  • Insert RAM_CONF parameter than need to be set inside local.conf file at build time

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Commit: edgehog/infrastructure/gitlab-ci@8b01f45d

[CUSTOM] Add custom project to gitlab-ci deploy

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Commit: edgehog/infrastructure/gitlab-ci@6566ad42

[BOARDS][CONFIG] Insert configs for C61, D18, D23

  • Insert configuration file for C61 iMX8MM SBC board
  • Insert configuration file for D18 iMX8MP SMARC board
  • Insert configuration file for D23 PX30 SBC board
  • Use same ssstate-cache folder of C31 SBC for D23 SBC

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Commit: edgehog/infrastructure/gitlab-ci@bc54e54b

[BITBAKE][CONF] Optimize parameters for the build

  • Insert the parameter BB_NUMBER_THREADS defining the maximum number of tasks BitBake should run in parallel at any one time (default set to 64).
  • Insert the parameter PARALLEL_MAKE specifying extra options that are passed to the make command during the compile tasks (default set to 64).

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Commit: edgehog/infrastructure/gitlab-ci@556c42f9

[TEST] Fix on token to attach to image string

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Commit: edgehog/infrastructure/gitlab-ci@cd91dc06

[CUSTOM][TEST] Fix on token reference name

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Commit: edgehog/infrastructure/gitlab-ci@4429d173

[CHANGELOG] Add BSP MR reference

  • Include a list of repositories whose name appears in the MR on meta-layers regarding BSP changes
  • Include this MR from Gitbot because they bring information regarding the BSP itself

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Commit: edgehog/infrastructure/gitlab-ci@abd19aaa

Merge branch 'probe_test' of git.seco.com:edgehog/infrastructure/gitlab-ci into probe_test

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Commit: edgehog/infrastructure/gitlab-ci@cbf55108

[CHANGELOG] Remove linux-imx repository reference

  • The Edgehog project is not using anymore the forked repository but the original one in GitHub

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Commit: edgehog/infrastructure/gitlab-ci@b3de77f2

[A62] Update CI_PARAM_TEST_SUITE value

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Commit: edgehog/infrastructure/gitlab-ci@ce8d8d8d

[TEST] Add CI_PARAM_TEST_SUITE

  • Parameter necessary to submit test job

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Commit: edgehog/infrastructure/gitlab-ci@4aa45124

[TESTING] Add test-probe stage

  • First implementation of LAVA testing of Edgehog Embedded Full Image
  • First support for A62, C20, C26, C43, C12
  • The test is executed every time a new build is executed by triggering it manually or on schedule (allow to fail rule)
  • Change rule for deploy, changelog to manually run on MR

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Commit: edgehog/infrastructure/gitlab-ci@eec919bf

[CACHE] Avoid sstate-cache usage for Intel

  • An error in compiling .wic image is given when building Intel Apollo Lake image

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Commit: edgehog/infrastructure/gitlab-ci@bb022e9c

[BUILD] Remove error on dtbo artifacts not found

  • This is necessary since seco-ne boards does not have .dtbo but only .dtb

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