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Integrate meta-seco-imx/linux-seco-imx/seco_lf-5.10.y-pll14xx-ssc

GitBot requested to merge integrate/meta-seco-imx/linux-seco-imx/seco_lf-5.10.y-pll14xx-ssc/into/kirkstone into kirkstone

Commit: edgehog/layers/seco/meta-seco-imx@cc374b67

Integrate linux-seco-imx/seco_lf-5.10.y-pll14xx-ssc

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Commit: edgehog/bsp/nxp/linux-seco-imx@23ee9c0f

[DRIVER] clk: imx: pll1443x: add PLL SSCG support

In some situations, users might face EMI issues due to spikes around specific frequencies: enabling Spread Spectrum Clocking is indicated to reduce the electromagnetic peak around that specific frequency.

From the i.MX8MP SoC Reference Manual document, Section 5.1.8 "CCM Analog Memory Map/Register Definition", the DRAM PLL, Audio PLL1, Audio PLL2 and Video PLL1 have available the spread spectrum function.

The spread spectrum mode parameters of these PLLs can be calculated using the formulas below:

  • Modulation frequency: MF = Fin / p / mfr / (2^5) [Hz]
  • Modulation rate: MR = mfr * mrr / m / (2^6) × 100 [%: percentage of the PLL output frequency]
  • Where:
    • 0 <= mfr <= 255, 1 <= mrr <= 63, 0 <= mrr × mfr <= 512
    • Fin - PLL input clock frequency (typically, 24MHz = 24 * (10^6) Hz)
    • p = CCM_ANALOG_XXX_YYY_FDIV_CTL0[PLL_PRE_DIV] - reference frequency pre-divider value
    • m = CCM_ANALOG_XXX_YYY_FDIV_CTL0[PLL_MAIN_DIV] - PLL main divider value
    • mfr = CCM_ANALOG_XXX_YYY_SSCG_CTRL[PLL_MFREQ_CTL] - modulation frequency factor
    • mrr = CCM_ANALOG_XXX_YYY_SSCG_CTRL[PLL_MRAT_CTL] - modulation range factor

fsl,imx8mm-anatop optional properties:

  • anatop-<$1>,sscg-enable
    • type: boolean
    • <$1>: PLL clk name
    • description: enable SSCG
  • anatop-<$1>,mfr
    • type: u32
    • <$1>: PLL clk name
    • description: modulation frequency control value
  • anatop-<$1>,mrr
    • type: u32
    • <$1>: PLL clk name
    • description: modulation rate control value
  • anatop-<$1>,sel-pf
    • type: u32
    • <$1>: PLL clk name
    • description: modulation method control value

fsl,imx8mm-anatop dts example: &anatop { anatop-video_pll1,sscg-enable; anatop-video_pll1,mfr = <12>; anatop-video_pll1,mrr = <14>; anatop-video_pll1,sel-pf = <2>; };

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Commit: edgehog/bsp/nxp/linux-seco-imx@6714a8fa

[DRIVER] clk: imx: pll14xx: fix and use macros for FDIV_CTL regs

Correct the definitions of "Divide and Fraction Data Control" registers, and use them in the appropriate code sections.

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