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Integrate meta-seco-rk/u-boot-seco_2017_09_next/ap/fix-dp83867-driver

Commit: https://git.seco.com/edgehog/layers/seco/meta-seco-rk/-/commit/b5d397b38253e0469afcaf383a4755b2e5620b8d

Integrate u-boot-seco-rk/ap/fix-dp83867-driver

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/996ee5afd12b9aa50626f63def1e685e6bdc9509

[DRIVERS] Enable support for setting up DP83867 leds

Based on kernel commit https://git.seco.com/edgehog/bsp/rockchip/linux-seco-rk/-/commit/36e6025f973d3f312544bb4aa99001c42a23989d?merge_request_iid=51

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/438ca97e8036b3ffe83328710a0749aeae56a0cb

[DRIVERS] net: phy: dp83867: rework delay rgmii delay handling

Based on this commit: https://git.seco.com/edgehog/bsp/nxp/u-boot-seco-imx/-/commit/20f7ea4c35ff98003c29eec442700af04496b49f

Based on commit c11669a2757e ("net: phy: dp83867: Rework delay rgmii delay handling") of mainline linux kernel.

The current code is assuming the reset default of the delay control register was to have delay disabled. This is what the datasheet shows as the register's initial value. However, that's not actually true: the default is controlled by the PHY's pin strapping.

This patch:

  • insures the other direction's delay is disabled If the interface mode is selected as RX or TX delay only
  • validates the delay values and fail if they are not in range
  • checks if the board is strapped to have a delay and is configured to use "rgmii" mode and warning is generated that "rgmii-id" should have been used.

Signed-off-by: Grygorii Strashko grygorii.strashko@ti.com Acked-by: Joe Hershberger joe.hershberger@ni.com

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/170c75687eef6f0860ef717f71c2e1b60d139c31

[DRIVERS] net: phy: dp83867: switch to use ofnode api

Based on: https://git.seco.com/edgehog/bsp/nxp/u-boot-seco-imx/-/commit/3ab75cf76e78d2ce729896625504cdfff1d3d8a5

Switch to use more generic ofnode API instead of FDT API.

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