Integrate u-boot-seco-rk/rk3588_cru_drm_dsi
Commit: edgehog/bsp/rockchip/u-boot-seco-rk@ad22de28
rockchip: rk3588: fix aclk_vop_root_sel to 3bit width
Reference to trm the aclk_vop_root_sel has 3bit width.
Change-Id: I2f87e427446f59d408dcf89ed175ddb95ae0a8fb Signed-off-by: Jianqun Xu jay.xu@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@4b369867
clk: rockchip: rk3588: Resync from kernel-5.10
Resync from kernel-5.10: (Iec7deb4005d clk: rockchip: rk3588: export clk_aux16m_x id for dp)
Signed-off-by: Zhang Yubing yubing.zhang@rock-chips.com Change-Id: I64bdee73f8bdaa3f9b77fa162f7555f21300838a
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@bc36ede9
clk: rockchip: match the kernel dclk clock scheme
Change-Id: I6082edbb3147b59029812c53f03598988cb62b54 Signed-off-by: Elaine Zhang zhangqing@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@13e8b5fe
clk: fix compile error with usbplug config
Signed-off-by: Yifeng Zhao yifeng.zhao@rock-chips.com Change-Id: I3776bb5bebc43857b38bbc4933aa5b584ffc97f6
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@0e9bf76a
clk: rockchip: rk3588: Avoid re-setting the pll rate of dclk_vop's parent
Change-Id: I9d250bdf2346789f81507b7dfe204fbede6c8ac4 Signed-off-by: Wyon Bi bivvy.bi@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@fc8acb5e
clk: rockchip: rk3588: support aclk_top_root set 750M
Change-Id: I78f00d37a645f37e28587d1c31f3179d5fa891e7 Signed-off-by: Elaine Zhang zhangqing@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@46b42d4d
clk: rk3588: Add 742.5M parameter for PLL
Change-Id: I5a842a3103df9a566789e7635fb484e4bb0bf427 Signed-off-by: Guochun Huang hero.huang@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@6f35349e
clk: rockchip: rk3588: fix unsigned compared against 0
Change-Id: I4e2e5a8a4524c2be2b53b8cea95f39d1d270a68b Signed-off-by: Jianqun Xu jay.xu@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@f96e1e38
clk: rockchip: rk3588: do coding style
Fix identical code for different branches.
Change-Id: Idd15347d5367bc4a3165046c23fb6e8ff0694fd9 Signed-off-by: Jianqun Xu jay.xu@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@c1a92933
clk: rockchip: rk3588: remove dead code
Change-Id: I1aa718b3ff637467321f05ae80eddd85a20bfc7b Signed-off-by: Jianqun Xu jay.xu@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@dea0a751
clk: rockchip: rk3588: do memset for clk structure
Change-Id: I229093ad350787fa60334b50ae9e4f48144bd46f Signed-off-by: Jianqun Xu jay.xu@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@7c58cf35
clk: rockchip: rk3588: fix copy-paster error
Change-Id: If3b2ce36f4f26530cf78c92bcfb01df8b4f63f09 Signed-off-by: Jianqun Xu jay.xu@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@fe63833c
clk: rockchip: rk3588: change cpul clock source to pvtpll
Change-Id: I4ab6d15c05b4cb805b60125cb5bb7e7d2e65d6e5 Signed-off-by: Finley Xiao finley.xiao@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@134e7fe4
clk: rockchip: rk3588: add wdt clk
Change-Id: I74634dc216b09400c1abe3fbf42106accf9f0108 Signed-off-by: Elaine Zhang zhangqing@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@bfaf9c10
clk: rk3588: Init the PPLL to 1.1G
The pcie2 combophy clk output will have better quality in this setting.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Change-Id: I9e312123a51d7f34c6c22780148f63d14c147442
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@8ca85e14
clk: rk3588: Add 1.1G parameter for PLL
PPLL may need to use 1.1G Hz.
Signed-off-by: Kever Yang kever.yang@rock-chips.com Change-Id: I81a86e0fe47c88a0aefced6502723a8469ec59e0
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@d1ba84b5
clk: rockchip: rk3588: fix up clk_pwm1 setting error
Signed-off-by: Damon Ding damon.ding@rock-chips.com Change-Id: I391357118f8f0c5fd55703ae9aaa27d64d63b173
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@3ef77f96
driver: fix the one display line error for vp3(DSI)
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@4f940d68
clk: rockchip: rk3588: support setting dp aux channel clk
Signed-off-by: Zhang Yubing yubing.zhang@rock-chips.com Change-Id: I65954d0805ce51c042dd5ca469781fb55ab1bccc
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@ef48228d
clk: rockchip: rk3588: set b0pll b1pll to 1200M in SPL
Change-Id: Idc47b57e940da7d9c4deeceba004bc5fc8d6c2ad Signed-off-by: Elaine Zhang zhangqing@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@445d873a
clk: rockchip: rk3588: Identify the dclk's parent by device name
Signed-off-by: Algea Cao algea.cao@rock-chips.com Change-Id: I6cb07de419eb0702a2b4445a059f96a44b7856c8
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@b4736651
clk: rockchip: rk3588: fix up dclk_vop3 setting error
Change-Id: I345a254f9adaf44d6dcd2bf37b4f429676643e44 Signed-off-by: Elaine Zhang zhangqing@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@316e57da
clk: rockchip: rk3588: Support hdmiphy pll
Signed-off-by: Algea Cao algea.cao@rock-chips.com Change-Id: I4fa787ed2b6057579985ab8469adef888eee1ee7
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@a458a3fb
clk: rockchip: rk3588: support aclk_vop to 850M
Change-Id: I1a42434e63e6fb6d55dc80827304e2c78ef3dcf1 Signed-off-by: Elaine Zhang zhangqing@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@a7276043
clk: rockchip: rk3588: Use scmi clk for cpub
Change-Id: Iac761088bd65d14f906fb0fe212d307b00f5d6c7 Signed-off-by: Finley Xiao finley.xiao@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@118ef5ce
video/drm: vop2: add half_block_en config for cluster wins
Signed-off-by: Damon Ding damon.ding@rock-chips.com Change-Id: Ic185c583921d8747122e490669da718fcb593215
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@3ab5dbe1
drm/rockchip: vop2: add support vop state to triggle DMC
Signed-off-by: Damon Ding damon.ding@rock-chips.com Change-Id: I5ef4b9b79197c909de32be0819c09c270da8ea39
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@caeddf15
video/drm: dsi2: set escape clk 20MHz default
solve no response when read back from panel in video mode display
Change-Id: I622e991929c09ae109cc500795e41073487a301c Signed-off-by: Guochun Huang hero.huang@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@a3ba8ceb
video/drm: dsi2: fix DSI_VID_TX_CFG configuration errors
Change-Id: Ib31f91fa7ab3b93388ad20410f5a773c10bc1315 Signed-off-by: Guochun Huang hero.huang@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@41369a05
video/drm: dsi2: use mode->crtc_clock instead of mode->clock to calculate
Change-Id: I026639eff059a66ab9deee913053dda1b03c0812 Signed-off-by: Guochun Huang hero.huang@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@c666a0b7
video/drm: dsi2: support specified lane rate by rockchip,lane-rate in Mbps/Kbps
Change-Id: I0cebc7a89b8e88fa463d44e41d80376faabac3be Signed-off-by: Guochun Huang hero.huang@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@1831d151
video/drm: dsi2: accurately set mipi channel rate to Kbps/Ksps level
Change-Id: Ie87c00d1e2e84df73fe7363247a2dd4ae0f8e5e3 Signed-off-by: Guochun Huang hero.huang@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@f01e8321
video/drm: dsi2: make horizontal scanning setup time more accurate
Change-Id: I2705a76c7a659913b06aa8d2829d855988ec9978 Signed-off-by: Guochun Huang hero.huang@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@16762a5c
drm/rockchip: vop2: support getting primary_plane_id from dts directly
Signed-off-by: Damon Ding damon.ding@rock-chips.com Change-Id: I636272c0ee3311785ed6b0d71fe3dab685aba07c
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@9de1eb03
drm/rockchip: rockchip_display: fix reserved logo memory align as PAGE(4096)
Signed-off-by: Sandy Huang hjc@rock-chips.com Change-Id: I37aae6730fcf15bc5c852274e21093addc6507cf
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@d868ae0e
video/drm: phy: dcphy: make Tskewcal maximum is 100 usec at initial calibration
Change-Id: I53c70f5108b2302ab5beed4b2dc9744ef730b913 Signed-off-by: Guochun Huang hero.huang@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@18b71353
video/drm: phy: dcphy: fix HSTX_CLK_SEL config
set HSTX_CLK_SEL 1b1 when cphy lane rate under 500Msps, while set HSTX_CLK_SEL 1b1 when dphy lane rate under 1500Mbps
Change-Id: I78138efde39c08337ae2de0f8098c0fb9435d359 Signed-off-by: Guochun Huang hero.huang@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@5f0cbb7b
video/drm: phy: dcphy: accurately set mipi channel rate to Kbps/Ksps level
take 1280x720@60Hz which pclk is 74.25Mhz as an example, the dsi lane rate should set 445500 Kbps/lane(pclk x bpp = lane_rate x lanes) when mipi work in no video burst pulse/event, therefore the PLL should output the rate of Kbps/ksps level for normal display.
Change-Id: Iba0118517462aa71fd18fafc42a0b5c0c190334d Signed-off-by: Guochun Huang hero.huang@rock-chips.com
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Commit: edgehog/bsp/rockchip/u-boot-seco-rk@8e5c3d2b
video/drm: phy: dcphy: use m_phy_rst to describe M_RESETN
M_RESETN: reset to PLL、TX Clock lane and data lane 0/1/2/3 block
Change-Id: I532c68361de19d88afefe701692030a284146c57 Signed-off-by: Guochun Huang hero.huang@rock-chips.com