Integrate u-boot-seco-rk/seco_2017.09_next_drm_dsi

Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/118ef5ce069544e783542788da4b20e9186274f4

video/drm: vop2: add half_block_en config for cluster wins

Signed-off-by: Damon Ding damon.ding@rock-chips.com Change-Id: Ic185c583921d8747122e490669da718fcb593215

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/3ab5dbe1451d4cecde4041b4266e4aecb487b7c0

drm/rockchip: vop2: add support vop state to triggle DMC

Signed-off-by: Damon Ding damon.ding@rock-chips.com Change-Id: I5ef4b9b79197c909de32be0819c09c270da8ea39

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/caeddf155e2ab0e7d073c1f51dd2347a8f050f38

video/drm: dsi2: set escape clk 20MHz default

solve no response when read back from panel in video mode display

Change-Id: I622e991929c09ae109cc500795e41073487a301c Signed-off-by: Guochun Huang hero.huang@rock-chips.com

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/a3ba8ceb0a1081870720aa5aecee6c3699d6a8bb

video/drm: dsi2: fix DSI_VID_TX_CFG configuration errors

Change-Id: Ib31f91fa7ab3b93388ad20410f5a773c10bc1315 Signed-off-by: Guochun Huang hero.huang@rock-chips.com

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/41369a05bbc89c16a22134e279ba8a46e4eb9518

video/drm: dsi2: use mode->crtc_clock instead of mode->clock to calculate

Change-Id: I026639eff059a66ab9deee913053dda1b03c0812 Signed-off-by: Guochun Huang hero.huang@rock-chips.com

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/c666a0b7d4de432a2aaa40cddd6ca26133d6dd14

video/drm: dsi2: support specified lane rate by rockchip,lane-rate in Mbps/Kbps

Change-Id: I0cebc7a89b8e88fa463d44e41d80376faabac3be Signed-off-by: Guochun Huang hero.huang@rock-chips.com

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/1831d151d1b1a9bfb1eef5eb13bd69eb3602b544

video/drm: dsi2: accurately set mipi channel rate to Kbps/Ksps level

Change-Id: Ie87c00d1e2e84df73fe7363247a2dd4ae0f8e5e3 Signed-off-by: Guochun Huang hero.huang@rock-chips.com

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/f01e8321b9165e4a00d20160e556569bed49889b

video/drm: dsi2: make horizontal scanning setup time more accurate

Change-Id: I2705a76c7a659913b06aa8d2829d855988ec9978 Signed-off-by: Guochun Huang hero.huang@rock-chips.com

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/16762a5cfe0b9f2017fc0712cbb8030fab60db18

drm/rockchip: vop2: support getting primary_plane_id from dts directly

Signed-off-by: Damon Ding damon.ding@rock-chips.com Change-Id: I636272c0ee3311785ed6b0d71fe3dab685aba07c

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/9de1eb0347edaf42811c89f3a63fc2c6e0e93e37

drm/rockchip: rockchip_display: fix reserved logo memory align as PAGE(4096)

Signed-off-by: Sandy Huang hjc@rock-chips.com Change-Id: I37aae6730fcf15bc5c852274e21093addc6507cf

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/d868ae0e71b622c42610ce96437c3ab94a67cba0

video/drm: phy: dcphy: make Tskewcal maximum is 100 usec at initial calibration

Change-Id: I53c70f5108b2302ab5beed4b2dc9744ef730b913 Signed-off-by: Guochun Huang hero.huang@rock-chips.com

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/18b71353f2ec7963aec00d4a3ad768b8d741bd45

video/drm: phy: dcphy: fix HSTX_CLK_SEL config

set HSTX_CLK_SEL 1b1 when cphy lane rate under 500Msps, while set HSTX_CLK_SEL 1b1 when dphy lane rate under 1500Mbps

Change-Id: I78138efde39c08337ae2de0f8098c0fb9435d359 Signed-off-by: Guochun Huang hero.huang@rock-chips.com

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/5f0cbb7bc51926bb690ce7000b850012210f70e2

video/drm: phy: dcphy: accurately set mipi channel rate to Kbps/Ksps level

take 1280x720@60Hz which pclk is 74.25Mhz as an example, the dsi lane rate should set 445500 Kbps/lane(pclk x bpp = lane_rate x lanes) when mipi work in no video burst pulse/event, therefore the PLL should output the rate of Kbps/ksps level for normal display.

Change-Id: Iba0118517462aa71fd18fafc42a0b5c0c190334d Signed-off-by: Guochun Huang hero.huang@rock-chips.com

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Commit: https://git.seco.com/edgehog/bsp/rockchip/u-boot-seco-rk/-/commit/8e5c3d2b08e8fc9a45bec5958ef3ca54ad58801a

video/drm: phy: dcphy: use m_phy_rst to describe M_RESETN

M_RESETN: reset to PLL、TX Clock lane and data lane 0/1/2/3 block

Change-Id: I532c68361de19d88afefe701692030a284146c57 Signed-off-by: Guochun Huang hero.huang@rock-chips.com