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Commit cc10b6c5 authored by Davide Cardillo's avatar Davide Cardillo
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MACHINE][C31] Add basic support for C31 SBC


This board is based on Rk3399 SOC.

Log of a boot of core-image-minimal image:

DDR Version 1.30 20230417
In
channel 0
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 1
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 0 training pass!
channel 1 training pass!
change freq to 416MHz 0,1
Channel 0: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
Channel 1: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
256B stride
channel 0
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 1
CS = 0
MR0=0x98
MR4=0x1
MR5=0xFF
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 0 training pass!
channel 1 training pass!
channel 0, cs 0, advanced training done
channel 1, cs 0, advanced training done
change freq to 856MHz 1,0
ch 0 ddrconfig = 0x101, ddrsize = 0x20
ch 1 ddrconfig = 0x101, ddrsize = 0x20
pmugrf_os_reg[2] = 0x3281F281, stride = 0x9
ddr_set_rate to 328MHZ
ddr_set_rate to 666MHZ
ddr_set_rate to 928MHZ
channel 0, cs 0, advanced training done
channel 1, cs 0, advanced training done
ddr_set_rate to 416MHZ, ctl_index 0
ddr_set_rate to 856MHZ, ctl_index 1
support 416 856 328 666 928 MHz, current 856MHz
OUT
Boot1 Release Time: May 29 2020 17:36:36, version: 1.26
CPUId = 0x0
ChipType = 0x10, 640
SdmmcInit=2 0
BootCapSize=100000
UserCapSize=15028MB
FwPartOffset=2000 , 100000
mmc0:cmd5,20
SdmmcInit=0 0
BootCapSize=0
UserCapSize=14910MB
FwPartOffset=2000 , 0
StorageInit ok = 72865
SecureMode = 0
SecureInit read PBA: 0x4
SecureInit read PBA: 0x404
SecureInit read PBA: 0x804
SecureInit read PBA: 0xc04
SecureInit read PBA: 0x1004
SecureInit read PBA: 0x1404
SecureInit read PBA: 0x1804
SecureInit read PBA: 0x1c04
SecureInit ret = 0, SecureMode = 0
atags_set_bootdev: ret:(0)
GPT part:  0, name:            uboot, start:0x4000, size:0x2000
GPT part:  1, name:            trust, start:0x6000, size:0x2000
GPT part:  2, name:           bootfs, start:0x8000, size:0x1ca5e
GPT part:  3, name:           rootfs, start:0x28000, size:0x10490
find part:uboot OK. first_lba:0x4000.
find part:trust OK. first_lba:0x6000.
Trust Addr:0x6000, 0x58334c42
No find bl30.bin
Load uboot, ReadLba = 4000
Load OK, addr=0x200000, size=0x11d5c0
RunBL31 0x40000 @ 308341 us
NOTICE:  BL31: v1.3(release):8f40012ab
NOTICE:  BL31: Built : 14:20:53, Feb 16 2023
NOTICE:  BL31: Rockchip release version: v1.1
INFO:    GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3
INFO:    Using opteed sec cpu_context!
INFO:    boot cpu mask: 0
INFO:    plat_rockchip_pmu_init(1203): pd status 3e
INFO:    BL31: Initializing runtime services
INFO:    BL31: Initializing BL32
INF [0x0] TEE-CORE:init_primary_helper:337: Initializing (1.1.0-278-gef70f120a #zhangzj #9 Fri Sep
17 09:39:24 UTC 2021 aarch64)

INF [0x0] TEE-CORE:init_primary_helper:338: Release version: 1.2

INF [0x0] TEE-CORE:init_teecore:83: teecore inits done
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x200000
INFO:    SPSR = 0x3c9

U-Boot 2017.09 (Sep 02 2024 - 11:58:49 +0000)

Model: Rockchip RK3399 SECO Board (C31)
PreSerial: 2, raw, 0xff1a0000
DRAM:  2 GiB
Sysmem: init
Relocation Offset: 7db68000
Relocation fdt: 7bd50978 - 7bd5ec57
CR: M/C/I
I2c0 speed: 400000Hz
PMIC:  RK808
vdd_center 900000 uV
vdd_cpu_l 900000 uV
I2c5 speed: 400000Hz
PCIe link training gen1 timeout!
board_pcie_device_probe PCI INTEL_I210_COPPER device not found
MMC:   dwmmc@fe320000: 1, sdhci@fe330000: 0
*** Warning - bad CRC, using default environment

Model: Rockchip RK3399 SECO Board (C31)
I2c4 speed: 100000Hz
switch to partitions #0, OK
mmc1 is current device
Bootdev(atags): mmc 1
MMC1: Legacy, 52Mhz
PartType: EFI
No misc partition
boot mode: None
CLK: (uboot. arml: enter 400000 KHz, init 816000 KHz, kernel 0N/A)
CLK: (uboot. armb: enter 24000 KHz, init 816000 KHz, kernel 0N/A)
  aplll 816000 KHz
  apllb 816000 KHz
  dpll 856000 KHz
  cpll 24000 KHz
  gpll 800000 KHz
  npll 600000 KHz
  vpll 24000 KHz
  aclk_perihp 133333 KHz
  hclk_perihp 66666 KHz
  pclk_perihp 33333 KHz
  aclk_perilp0 266666 KHz
  hclk_perilp0 88888 KHz
  pclk_perilp0 44444 KHz
  hclk_perilp1 100000 KHz
  pclk_perilp1 50000 KHz
No misc partition
Net:   eth0: ethernet@fe300000
Start boot...
Hit key to stop autoboot('CTRL+C'):  0
switch to partitions #0, OK
mmc1 is current device
** File not found seco_boot.scr **
==> Running in Normal Mode...
switch to partitions #0, OK
mmc1 is current device
35676672 bytes read in 1475 ms (23.1 MiB/s)
99612 bytes read in 11 ms (8.6 MiB/s)
Ramdisk skip relocation
No misc partition
   Booting using the fdt blob at 0x08300000
   reserving fdt memory region: addr=8300000 size=d9000
  'reserved-memory' ramoops@8000000: addr=8000000 size=d0000
   Loading Device Tree to 000000007bc73000, end 000000007bd4efff ... OK
Adding bank: 0x00200000 - 0x08400000 (size: 0x08200000)
Adding bank: 0x0a200000 - 0x80000000 (size: 0x75e00000)
Total: 8018.279 ms

Starting kernel ...

[    8.127346] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    8.127376] Linux version 5.10.110 (oe-user@oe-host) (aarch64-poky-linux-gcc (GCC) 13.3.0, GNU l
d (GNU Binutils) 2.42.0.20240216) #1 SMP Wed Sep 4 13:53:08 UTC 2024
[    8.134238] Machine model: Rockchip RK3399 SECO Board (C31)
...

SECO Clea OS Distro 5.0.2 seco-rk3399-c31 /dev/ttyFIQ0

seco-rk3399-c31 login:

Signed-off-by: default avatarDavide Cardillo <davide.cardillo@seco.com>
parent 2eb63b0b
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1 merge request!307[LAYER] PX30 and RK platforms support compatible with Clea OS
#@TYPE: Machine
#@NAME: RK3399 SECO SBC C31
require conf/machine/include/rk3399.inc
# #### U-BOOT CONFIGURATION ####
UBOOT_MAKE_TARGET = ""
UBOOT_MACHINE = "seco_rk3399_c31_defconfig"
# #### KERNEL CONFIGURATION ####
KBUILD_DEFCONFIG = "seco_linux_defconfig"
KERNEL_DTB_FILES = " \
seco-rk3399-c31.dtb \
"
KERNEL_DTB_OVERLAY_FILES = " \
seco-rk3399-c31-can1.dtbo \
seco-rk3399-c31-can2.dtbo \
seco-rk3399-c31-rtc.dtbo \
seco-rk3399-c31-flash.dtbo \
seco-rk3399-c31-rs485.dtbo \
seco-rk3399-c31-gpio.dtbo \
seco-rk3399-c31-hdmi-vopL.dtbo \
seco-rk3399-c31-hdmi-vopB.dtbo \
seco-rk3399-c31-edp-vopB.dtbo \
seco-rk3399-c31-edp-vopL.dtbo \
seco-rk3399-c31-lvds-vopB.dtbo \
seco-rk3399-c31-lvds-vopL.dtbo \
seco-rk3399-c31-typec-dp-vopB.dtbo \
seco-rk3399-c31-typec-dp-vopL.dtbo \
"
\ No newline at end of file
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