Integrate gitlab-ci/lpag/new_board_config and 19 more

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/e88df1a2c5b94e22d2aa2ce4019e8e760fe09e24

[BOARD][CONFIG] Insert config for TigerLake boards

• Insert configuration file for boards based on Intel Tiger Lake boards

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/944f20d931dc32d35191af6ef1f7a347082bf9e7

[NUM_MAX_CPU] Reduce the number of CPU threads

• Set the number to 32 and increase number of parallel jobs for the runner

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/4a79ac2be80fbc3b4df8131788e7321735bb7cb3

[TIMEOUT] Increase timeout on notify/changelog job

• Increase the timeout to 4h because of increased overload on CI/CD pipeline

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/d710ecdbdb8e8aa5674d284f43f04fffff156c9a

[BOARD][CONFIG] Insert config for c72n board

• Remove c61 config file since not released yet

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/bf6989583a1aabc1a9e697039614923098db689b

[928] Fix on 8x512M RAM configuration file

• Fix on AZURE_PATH variable position

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/e24139724cc9eb592ec7fa04c4f0395d3919fc36

[962] Add 962 i.MX6 board configuration file

• The configuration file allows to build 3 different RAM configurations: 2x256M, 4x256M, 4x512M
• Insert preliminary test integration job

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/6de4af636868c0872f8c503c8340e22e28d10752

[BOARD][CONFIG] Insert config for 928 board

• Add configuration file for 928 considering all the supported RAM configurations
• Insert RAM_CONF parameter than need to be set inside local.conf file at build time

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/8b01f45d6f24e51f1df9c95d3018f1f74f08b48d

[CUSTOM] Add custom project to gitlab-ci deploy

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/6566ad420f1b9300fe395fd988fc1a6e5225d0eb

[BOARDS][CONFIG] Insert configs for C61, D18, D23

• Insert configuration file for C61 iMX8MM SBC board
• Insert configuration file for D18 iMX8MP SMARC board
• Insert configuration file for D23 PX30 SBC board
• Use same ssstate-cache folder of C31 SBC for D23 SBC

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/bc54e54b7fcb0284539d7c8b72969954d082ce37

[BITBAKE][CONF] Optimize parameters for the build

• Insert the parameter BB_NUMBER_THREADS defining the maximum number of tasks BitBake should run in parallel at any one time (default set to 64).
• Insert the parameter PARALLEL_MAKE specifying extra options that are passed to the make command during the compile tasks (default set to 64).

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/556c42f9aa67a7ad40c25554a6fb211e8064e55a

[TEST] Fix on token to attach to image string

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/cd91dc063b4084421e5fc2bc289859a09549ab56

[CUSTOM][TEST] Fix on token reference name

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/4429d173a7db3d6d3753a6e567923f8e8ad9488b

[CHANGELOG] Add BSP MR reference

• Include a list of repositories whose name appears in the MR on meta-layers regarding BSP changes
• Include this MR from Gitbot because they bring information regarding the BSP itself

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/abd19aaac279c92e61fba72b65fdc2ea7caff5de

Merge branch 'probe_test' of git.seco.com:edgehog/infrastructure/gitlab-ci into probe_test

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/cbf55108728afc98400cd18135a956098f9076bc

[CHANGELOG] Remove linux-imx repository reference

• The Edgehog project is not using anymore the forked repository but the original one in GitHub

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/b3de77f23c31a400a4d4b4b96e7b96901e53e588

[A62] Update CI_PARAM_TEST_SUITE value

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/ce8d8d8dc14b68f45099663680cd0baee572ac4c

[TEST] Add CI_PARAM_TEST_SUITE

• Parameter necessary to submit test job

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/4aa451241f39cf2d911640f08130a79df46d4655

[TESTING] Add test-probe stage

• First implementation of LAVA testing of Edgehog Embedded Full Image
• First support for A62, C20, C26, C43, C12
• The test is executed every time a new build is executed by triggering it manually or on schedule (allow to fail rule)
• Change rule for deploy, changelog to manually run on MR

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/eec919bff8c6ea5f5d72d23543233623defac20b

[CACHE] Avoid sstate-cache usage for Intel

• An error in compiling .wic image is given when building Intel Apollo Lake image

--

Commit: https://git.seco.com/edgehog/infrastructure/gitlab-ci/-/commit/bb022e9c0264a173cd29ab9d3b60e43e7043491a

[BUILD] Remove error on dtbo artifacts not found

• This is necessary since seco-ne boards does not have .dtbo but only .dtb