Integrate linux-seco-imx/seco_lf-5.10.y-pll14xx-ssc

Commit: edgehog/bsp/nxp/linux-seco-imx@d8131848

[DRIVER] clk: imx: pll1443x: add PLL SCCG support

anatop node: dts properties:

• anatop-<$1>,sscg-enable
  • type: boolean
  • <$1>: PLL clk name
  • description: enable SSCG
• anatop-<$1>,mfr
  • type: u32
  • <$1>: PLL clk name
  • description: modulation frequency factor value
• anatop-<$1>,mfr
  • type: u32
  • <$1>: PLL clk name
  • description: modulation range factor value
• anatop-<$1>,sel-pf
  • type: u32
  • <$1>: PLL clk name
  • description: modulation method control value

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Commit: edgehog/bsp/nxp/linux-seco-imx@a1e1cc59

[DRIVER] clk: imx: pll14xx: fix and use macros for FDIV_CTL regs

Correct the definitions of "Divide and Fraction Data Control" registers, and use them in the appropriate code sections.