[E60][DTS] Add gpio banks (0, 1, 2, 3, 4) with line names

arch/arm64/boot/dts/seco/seco-rk3588-e60.dtsi

@@ -500,6 +500,81 @@ regulator-state-mem {
 	};
 };
 
+&gpio0 {
+	gpio-line-names =
+	/* A0 */ "",              /* A1 */ "TSADC_SHUT_H",    /* A2 */ "PMIC_PWR_CTRL1",      /* A3 */ "CPU_BIG0_VSEL",
+	/* A4 */ "SDMMC_DET_L",   /* A5 */ "PMIC_SPI_CLK",    /* A6 */ "PMIC_SPI_MOSI",       /* A7 */ "PMIC_INT_L",
+
+	/* B0 */ "",              /* B1 */ "PMIC_SPI_CS",     /* B2 */ "",                    /* B3 */ "PMIC_MISO",
+	/* B4 */ "",              /* B5 */ "UART2_TX_DBG",    /* B6 */ "UART2_RX_DBG",        /* B7 */ "CAN0_TX",
+
+	/* C0 */ "CAN0_RX",       /* C1 */ "NPU_VSEL",        /* C2 */ "PCIE_TRITON_RST#",    /* C3 */ "PMIC_PWR_CTRL2",
+	/* C4 */ "UART0_RX",      /* C5 */ "UART0_TX",        /* C6 */ "UART0_RTS",           /* C7 */ "PCIE_TRITON_BUT_RST#",
+
+	/* D0 */ "SPI3_MISO",     /* D1 */ "UART0_CTS",       /* D2 */ "SPI3_MOSI",           /* D3 */ "SPI3_CLK",
+	/* D4 */ "SPI3_CS0",      /* D5 */ "IO_EXP_INT#",     /* D6 */ "CPU_BIG1_VSEL",       /* D7 */ "";
+};
+
+&gpio1 {
+	gpio-line-names =
+	/* A0 */"UART6_RX",       /* A1 */ "UART6_TX",        /* A2 */ "UART6_RTS",           /* A3 */ "UART6_CTS",
+	/* A4 */"CPU_GPIO5",      /* A5 */ "HDMI_TX0_HPD",    /* A6 */ "HDMI_TX1_HPD",        /* A7 */ "ESP_BLKT_CTRL",
+
+	/* B0 */"GP_WAKE#",       /* B1 */ "GP_SPI_MISO",     /* B2 */ "GP_SPI_MOSI",         /* B3 */ "GP_SPI_CLK",
+	/* B4 */"GP_SPI_CS0#",    /* B5 */ "GP_SPI_CS1#",     /* B6 */ "UART1_TX",            /* B7 */ "UART1_RX",
+
+	/* C0 */"I2C3_SDA",       /* C1 */ "I2C3_SCL",        /* C2 */ "I2C6_SDA",            /* C3 */ "I2C6_SCL",
+	/* C4 */"I2C_CAM1_DAT",   /* C5 */ "I2C_CAM1_CK",     /* C6 */ "I2C4_SDA",            /* C7 */ "I2C4_SCL",
+
+	/* D0 */"CAM0_PWR#",      /* D1 */ "CAM1_PWR#",       /* D2 */ "I2C_CAM0_DAT",        /* D3 */ "I2C_CAM0_CK",
+	/* D4 */"CAM0_RST#",      /* D5 */ "CAM1_RST#",       /* D6 */ "UART1_RTS",           /* D7 */ "UART1_CTS";
+};
+
+&gpio2 {
+	gpio-line-names =
+	/* A0 */ "eMMC_CMD",           /* A1 */ "eMMC_CLK",             /* A2 */ "eMMC_DATA_STROBE",     /* A3 */ "eMMC_RST#",
+	/* A4 */ "",                   /* A5 */ "",                     /* A6 */ "GMAC1_RXD2",           /* A7 */ "GMAC1_RXD3",
+
+	/* B0 */ "GMAC1_RXCLK",        /* B1 */ "GMAC1_TXD2",           /* B2 */ "GMAC1_TXD3",           /* B3 */ "GMAC1_TXCLK",
+	/* B4 */ "RTC_INT#",           /* B5 */ "CPU_WAKE#",            /* B6 */ "GMAC1_TXD0",           /* B7 */ "GMAC1_TXD1",
+
+	/* C0 */ "GMAC1_TXEN",         /* C1 */ "GMAC1_RXD0",           /* C2 */ "GMAC1_RXD1",           /* C3 */ "RAM_STRAP_1",
+	/* C4 */ "RAM_STRAP_2",        /* C5 */ "RAM_STRAP_3",          /* C6 */ "",                     /* C7 */ "",
+
+	/* D0 */ "eMMC_D0",            /* D1 */ "eMMC_D1",              /* D2 */ "eMMC_D2",              /* D3 */ "eMMC_D3",
+	/* D4 */ "eMMC_D4",            /* D5 */ "eMMC_D5",              /* D6 */ "eMMC_D6",              /* D7 */ "eMMC_D7";
+};
+
+&gpio3 {
+	gpio-line-names =
+	/* A0 */ "FSPI_D0",            /* A1 */ "FSPI_D1",              /* A2 */ "FSPI_D2",              /* A3 */ "FSPI_D3",
+	/* A4 */ "EDP _BLK_EN",        /* A5 */ "FSPI_CLK",             /* A6 */ "TPM_RST#",             /* A7 */ "CPU_PWM0",
+
+	/* B0 */ "CPU_PWM1",           /* B1 */ "CPU_PWM2",             /* B2 */ "I2S2_SDI0",            /* B3 */ "I2S2_SDO0",
+	/* B4 */ "I2S2_MCLK",          /* B5 */ "I2S2_SCLK",            /* B6 */ "I2S2_LRCLK",           /* B7 */ "SMB_ALERT#",
+
+	/* C0 */ "UART7_TX",           /* C1 */ "UART7_RX",             /* C2 */ "UART7_RTS",            /* C3 */ "UART7_CTS",
+	/* C4 */ "FSPI_CS0##",         /* C5 */ "EDP_VDD_EN",           /* C6 */ "IO_EXP_RST#",          /* C7 */ "I2C5_SCL",
+
+	/* D0 */ "I2C5_SDA",           /* D1 */ "ETH0_RST#",            /* D2 */ "I2C_SCL_COMe",         /* D3 */ "I2C_SDA_COMe",
+	/* D4 */ "ETH0_INT#",          /* D5 */ "DP1_HPD",              /* D6 */ "",                     /* D7 */ "";
+};
+
+&gpio4 {
+	gpio-line-names =
+	/* A0 */ "CPU_GPIO0",             /* A1 */ "CPU_GPIO1",            /* A2 */ "CPU_GPIO2",            /* A3 */ "CPU_GPIO3",
+	/* A4 */ "CPU_GPIO4",             /* A5 */ "UART3_TX",             /* A6 */ "UART3_RX",             /* A7 */ "PCIE_WAKE#",
+
+	/* B0 */ "PCIE_CLK_GEN_PWD",      /* B1 */ "TPM_IRQ#",             /* B2 */ "CAN1_RX",              /* B3 */ "CAN1_TX",
+	/* B4 */ "DP0_HPD",               /* B5 */ "CPU_PWM3",             /* B6 */ "SATA0_ACT",            /* B7 */ "HDMI_TX0_DDC_SCL_M0",
+
+	/* C0 */ "HDMI_TX0_DDC_SDA_M0",   /* C1 */ "PCIE30_CLK_GEN_OE#",   /* C2 */ "GMAC1_RXDV_CRS",       /* C3 */ "PCIE20_CLK_GEN_OE",
+	/* C4 */ "GMAC1_MDC",             /* C5 */ "GMAC1_MDIO",           /* C6 */ "USB4_RT_EN",           /* C7 */ "",
+
+	/* D0 */ "SDMMC_D0",              /* D1 */ "SDMMC_D1",             /* D2 */ "SDMMC_D2",             /* D3 */ "SDMMC_D3",
+	/* D4 */ "SDMMC_CMD",             /* D5 */ "SDMMC_CLK",            /* D6 */ "",                     /* D7 */ "";
+};
+
 /************************************************************************************
  * Based on rockchip rk3588-linux                                                   *
  ************************************************************************************/