arch/arm64/boot/dts/seco/include/baseboard-e81-b79.dtsi

@@ -105,4 +105,44 @@ gpio_usb3_en_oc_n {
 	};
 };
 
+
+&i2c1 {
+	postcode: ht16k33@71 {
+		compatible = "holtek,ht16k33";
+		reg = <0x71>;
+		refresh-rate-hz = <10>;
+		status = "disabled";
+		// Disabled by default, as it gets attached
+		// as /dev/fb0 and breaks the splash screen
+	};
+
+	hwmon: tmp102@49 {
+		compatible = "ti,tmp102";
+		reg = <0x49>;
+		status = "okay";
+	};
+
+	current_sense: ina219@40 {
+		compatible = "ti,ina219";
+		reg = <0x40>;
+		// shunt-resistor = <60000>; /* = 60 mOhms */
+	};
+};
+
+&i2c2 {
+	charger: ltc4100@9 {
+		compatible = "lltc,ltc4100", "sbs,sbs-charger";
+		reg = <0x9>;
+		status = "okay";
+	};
+
+	eeprom: eeprom@57 {
+		compatible = "atmel,24c32";
+		reg = <0x57>;
+		pagesize = <32>;
+		vcc-supply = <&reg_1v8>;
+		status = "okay";
+	};
+};
+
 #endif

arch/arm64/boot/dts/seco/include/display-e81-edp.dtsi

@@ -4,7 +4,7 @@
  * Device-tree-file for eDP display on SECO-E81 modules
  * 
  * based on
- * https://git.codelinaro.org/clo/le/platform/vendor/opensource/display-devicetree/-/blob/display-kernel.qclinux.1.0.r2-rel/display/qcm6490-sde-display-rb3gen2.dtsi
+ * https://git.codelinaro.org/clo/le/platform/vendor/opensource/display-devicetree/-/blob/782d2f451783ddc7975497b35ad79d3a7256a8f8/display/qcm6490-sde-display-rb3gen2.dtsi
  *
  * Copyright 2025 SECO NE    Dietmar Muscholik <dietmar.muscholik@seco.com>
  *

arch/arm64/boot/dts/seco/include/e81-common.dtsi

@@ -30,6 +30,7 @@
 #include "../../qcom/qcm6490.dtsi" // includes qcom/sc7280.dtsi
 #include "../../qcom/pm7325.dtsi"
 #include "../../qcom/pm8350c.dtsi"
+#include "../../qcom/pmk8350.dtsi" // also for pmk7325
 
 #include "e81-pinfunc.h"
 
@@ -156,6 +157,13 @@ reg_qps615_rsex: rsex_qps {
 		vin-supply = <&reg_1v8_qps>;
 		regulator-enable-ramp-delay = <10000>;
 	};
+
+	can_clk: can-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <20000000>;
+		clock-output-names = "can-clk";
+	};
 };
 
 
@@ -654,6 +662,35 @@ &sdhc_1 {
 	status = "okay";
 };
 
+// spi
+&spi14 { // SPI 0
+	pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>, <&qup_spi14_cs1_gpio>;
+	pinctrl-names = "default";
+
+	cs-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>, <&tlmm 62 GPIO_ACTIVE_LOW>;
+	
+	status = "okay";
+};
+
+&spi3 { // SPI 1
+	status = "okay";
+};
+
+&spi12 { // SPI CAN
+	status = "okay";
+
+	can0: can@0 {
+		compatible = "microchip,mcp2518fd";
+		reg = <0>;
+		clocks = <&can_clk>;
+		spi-max-frequency = <5000000>;
+		interrupts-extended = <&tlmm 35 IRQ_TYPE_LEVEL_LOW>;
+		vdd-supply = <&vreg_l11c_3p3>;
+		xceiver-supply = <&vreg_l11c_3p3>;
+	};
+};
+
+
 // disable soundwire devices
 &swr0 {
 	status = "disabled";
@@ -914,6 +951,9 @@ eth1_pci_iommu_group: eth1_pci_iommu_group {
 	};
 };
 
+&pon_pwrkey {
+	status = "okay";
+};
 
 // pinctrl
 &pm8350c_gpios {
@@ -939,6 +979,9 @@ lcd0_bklt_pwm: lcd0_bklt_pwm {
 };
 
 &tlmm {
+	// Remove the <48 4> (spi12 pins), which is set in qcm6490.dtsi
+    gpio-reserved-ranges = <32 2>;
+
 	pcie1_reset_n: pcie1-reset-n-state {
 		pins = "gpio2";
 		function = "gpio";
@@ -947,6 +990,11 @@ pcie1_reset_n: pcie1-reset-n-state {
 		bias-disable;
 	};
 
+	qup_spi14_cs1_gpio: qup-spi14-cs1-gpio-state {
+		pins = "gpio62";
+		function = "gpio";
+	};
+
 	qps615_intn_wol {
 		eth0_intn_wol_sig: eth0_intn_wol_sig {
 			mux {

arch/arm64/boot/dts/seco/include/qcm6490-sde.dtsi

@@ -2,8 +2,7 @@
 /*
  * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  *
- * Taken from https://git.codelinaro.org/clo/le/platform/vendor/opensource/
- * display-devicetree/-/blob/display-kernel.qclinux.1.0.r2-rel/display/qcm6490-sde.dtsi
+ * Taken from https://git.codelinaro.org/clo/le/platform/vendor/opensource/display-devicetree/-/blob/73de1199f5cab251c44b39237e4d10d8dbf2275b/display/qcm6490-sde.dtsi
  *
  * only stuff the dtc complains about has been commented out
  * 

arch/arm64/configs/seco_qcs6490_defconfig

@@ -670,8 +670,7 @@ CONFIG_RPMSG_CTRL=m
 CONFIG_RPMSG_QCOM_GLINK_RPM=y
 CONFIG_RPMSG_QCOM_GLINK_SMEM=m
 CONFIG_RPMSG_QCOM_SMD=y
-CONFIG_SOUNDWIRE=y
-CONFIG_SOUNDWIRE_QCOM=y
+# CONFIG_SOUNDWIRE is not set
 CONFIG_SOC_BRCMSTB=y
 CONFIG_FSL_RCPM=y
 CONFIG_QCOM_AOSS_QMP=y
@@ -868,3 +867,36 @@ CONFIG_ARM64_PMEM=y
 CONFIG_MFD_SECO_STM32=y
 CONFIG_DP83867_PHY=m
 CONFIG_RTC_DRV_RV3028=y
+
+CONFIG_CHARGER_SBS=m
+
+CONFIG_AUXDISPLAY=y
+CONFIG_FB_SYS_FOPS=m
+CONFIG_FB_SYS_FILLRECT=m
+CONFIG_FB_SYS_COPYAREA=m
+CONFIG_FB_SYS_IMAGEBLIT=m
+CONFIG_FB_BACKLIGHT=m
+CONFIG_INPUT_MATRIXKMAP=m
+CONFIG_LEDS_CLASS=y
+CONFIG_NEW_LEDS=y
+CONFIG_LINEDISP=m
+CONFIG_PAHOLE_HAS_SPLIT_BTF=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_CHARLCD_BL_FLASH=y
+CONFIG_HT16K33=m
+
+CONFIG_EEPROM_AT24=m
+CONFIG_SENSORS_TMP102=m
+CONFIG_SENSORS_INA2XX=m
+
+CONFIG_CAN=y
+CONFIG_CAN_VCAN=y
+CONFIG_CAN_SLCAN=y
+CONFIG_CAN_DEV=y
+CONFIG_CAN_MCP251XFD=y
+CONFIG_CAN_DEBUG_DEVICES=y
+CONFIG_CAN_CALC_BITTIMING=y
+CONFIG_SPI_MT65XX=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPI_SLAVE=y
+