[E81][DTB] Enable Ethernet phys

arch/arm64/boot/dts/seco/include/qcs6490-e81-common.dtsi

@@ -121,17 +121,6 @@ vreg_qps615_rsex: rsex_qps {
 		enable-active-high;
 		regulator-enable-ramp-delay = <10000>;
 	};
-
-	vreg_3p3_upd: 3p3_upd {
-		compatible = "regulator-fixed";
-		regulator-name = "3p3_upd";
-		vin-supply = <&vreg_qps615_rsex>;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		enable-active-high;
-		regulator-enable-ramp-delay = <10000>;
-		regulator-always-on;
-	};
 };
 
 &apps_rsc {
@@ -265,6 +254,7 @@ vreg_l11b_1p504: ldo11 {
 			regulator-min-microvolt = <1504000>;
 			regulator-max-microvolt = <2000000>;
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-always-on;
 		};
 
 // according to schematics page 3+4 these regulators are to used
@@ -305,6 +295,7 @@ vreg_l17b_1p7: ldo17 {
 			regulator-min-microvolt = <1700000>;
 			regulator-max-microvolt = <1900000>;
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-always-on;
 		};
 
 		vreg_l18b_1p8: ldo18 {
@@ -726,6 +717,86 @@ pcieport0: pcie@0 {
 		reg = <0x0 0x0 0x0 0x0 0x0>;
 		#address-cells = <5>;
 		#size-cells = <0>;
+
+		/* BDF 1.0.0 */
+		pcie1_bus1_dev0_fn0: pcie1_bus1_dev0_fn0 {
+			reg = <0 0 0 0 0>;
+
+			/* BDF 2.1.0 */
+			pcie1_bus2_dev1_fn0: pcie1_bus2_dev1_fn0 {
+				reg = <0x800 0x0 0x0 0x0 0x0>;
+
+				/* BDF 3.0.0 */
+				pcie1_bus3_dev0_fn0: pcie1_bus3_dev0_fn0 {
+					reg = <0x0 0x0 0x0 0x0 0x0>;
+				};
+			};
+
+			/* BDF 2.2.0 */
+			pcie1_bus2_dev2_fn0: pcie1_bus2_dev2_fn0 {
+				reg = <0x1000 0x0 0x0 0x0 0x0>;
+
+				/* BDF 4.0.0 */
+				pcie1_bus4_dev0_fn0: pcie1_bus4_dev0_fn0 {
+					reg = <0x0 0x0 0x0 0x0 0x0>;
+				};
+			};
+
+			/* BDF 2.3.0 */
+			pcie1_bus2_dev3_fn0: pcie1_bus2_dev3_fn0 {
+				reg = <0x1800 0x0 0x0 0x0 0x0>;
+
+				// ETH0
+				qps615_eth0,qps615_eth0@pcie1_rp {
+					reg = <0x0 0x0 0x0 0x0 0x0>;
+					qcom,not-need-pinctrl;
+
+					/* phy intn_wol int */
+					qcom,phy-built-in-wol;
+
+					/* phy reset*/
+					qcom,phy-rst-gpio = <0>;
+					qcom,phy-rst-delay-us = <20000>;
+
+					/* power enable*/
+					phy-supply = <&vreg_l11b_1p504>;
+				};
+
+				/* BDF 5.0.0 */
+				pcie1_bus5_dev0_fn0: pcie1_qps_eth0 {
+					reg = <0x0 0x0 0x0 0x0 0x0>;
+					qcom,iommu-group = <&eth0_pci_iommu_group>;
+					eth0_pci_iommu_group: eth0_pci_iommu_group {
+						qcom,iommu-dma = "atomic";
+					};
+				};
+				
+				// ETH1
+				qps615_eth1,qps615_eth1@pcie1_rp {
+					reg = <0x100 0x0 0x0 0x0 0x0>;
+					qcom,not-need-pinctrl;
+
+					/* phy intn_wol int */
+					qcom,phy-built-in-wol;
+
+					/* phy reset*/
+					qcom,phy-rst-gpio = <1>;
+					qcom,phy-rst-delay-us = <20000>;
+					
+					/* power enable*/
+					phy-supply = <&vreg_l17b_1p7>;
+				};
+
+				/* BDF 5.0.1 */
+				pcie1_bus5_dev0_fn1: pcie1_qps_eth1 {
+					reg = <0x100 0x0 0x0 0x0 0x0>;
+					qcom,iommu-group = <&eth1_pci_iommu_group>;
+					eth1_pci_iommu_group: eth1_pci_iommu_group {
+						qcom,iommu-dma = "atomic";
+					};
+				};
+			};
+		};
 	};
 };