[E81][DTB] Enable PCIe0, PCIe1, QPS615

arch/arm64/boot/dts/seco/include/qcs6490-e81-common.dtsi

@@ -85,21 +85,20 @@ reg_0v9_qps: 0v9_qps {
 		regulator-name = "0V9_QPS";
 		regulator-min-microvolt = <900000>;
 		regulator-max-microvolt = <900000>;
-		//gpio = <&qps_0v9_en>;
 		gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
-		vin-supply = <&reg_5v_run>;
+		regulator-enable-ramp-delay = <4300>;
 	};
 
 	reg_1v8_qps: 1v8_qps {
 		compatible = "regulator-fixed";
 		regulator-name = "1V8_QPS";
+		vin-supply = <&reg_0v9_qps>;
 		regulator-min-microvolt = <1800000>;
 		regulator-max-microvolt = <1800000>;
-		//gpio = <&qps_1v8_en>;
 		gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
-		vin-supply = <&reg_5v_run>;
+		regulator-enable-ramp-delay = <10000>;
 	};
 
 	reg_3v3_wifi: 3v3_wifi {
@@ -110,6 +109,29 @@ reg_3v3_wifi: 3v3_wifi {
 		regulator-always-on;
 		vin-supply = <&reg_5v_run>;
 	};
+
+	// For some reason, qualcomm defines the reset-gpios in the regulator node
+	vreg_qps615_rsex: rsex_qps {
+		compatible = "regulator-fixed";
+		regulator-name = "rsex_qps";
+		vin-supply = <&reg_1v8_qps>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&pm8350c_gpios 1 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-enable-ramp-delay = <10000>;
+	};
+
+	vreg_3p3_upd: 3p3_upd {
+		compatible = "regulator-fixed";
+		regulator-name = "3p3_upd";
+		vin-supply = <&vreg_qps615_rsex>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		regulator-enable-ramp-delay = <10000>;
+		regulator-always-on;
+	};
 };
 
 &apps_rsc {
@@ -412,10 +434,22 @@ vreg_l11c_3p3: ldo11 {
 			regulator-max-microvolt = <3540000>;
 			regulator-always-on;
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
-		};
+		};	
 	};
 };
 
+// These are some clocks, required to be enabled here.
+// Otherwise, it won't even load the kernel.
+&gcc {
+	protected-clocks = <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>,
+			<GCC_QSPI_CORE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>,
+			<GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>,
+			<GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>,
+			<GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
+			<GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>,
+			<GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>;
+};
+
 // dma-controller
 &gpi_dma0 {
 	status = "okay";
@@ -452,6 +486,52 @@ &i2c13 { // TS_I2C
 	status = "okay";
 };
 
+// PCIe
+// PCIe 0 is external on carrier board
+&pcie0 {
+	perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&pcie0_phy {
+	status = "okay";
+	vdda-phy-supply = <&vreg_l10c_0v9>;
+	vdda-pll-supply = <&vreg_l6b_1p2>;
+};
+
+// PCIe 1 is connected to QPS615
+&pcie1 {
+	pinctrl-0 = <&pcie1_reset_n>, <&pcie1_clkreq_n>;
+	pinctrl-names = "default";
+	
+	perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+
+	// copied from qcom/qcs6490-rb3gen2.dts,
+	// but what does this mean?
+	iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+		    <0x100 &apps_smmu 0x1c81 0x1>,
+		    <0x208 &apps_smmu 0x1c84 0x1>,
+		    <0x210 &apps_smmu 0x1c85 0x1>,
+		    <0x218 &apps_smmu 0x1c86 0x1>,
+		    <0x300 &apps_smmu 0x1c87 0x1>,
+		    <0x400 &apps_smmu 0x1c88 0x1>,
+		    <0x500 &apps_smmu 0x1c89 0x1>,
+		    <0x501 &apps_smmu 0x1c90 0x1>;
+
+	status = "okay";
+};
+
+&pcie1_phy {
+	//vdda-phy-supply = <&vreg_l19b_1p8>;
+	vdda-phy-supply = <&vreg_l10c_0v9>;
+	vdda-pll-supply = <&vreg_l6b_1p2>;
+	qcom,refclk-always-on;
+
+	status = "okay";
+};
+
 // GENI Serial Engine QUP Wrapper Controller
 // (parent of all serial interfaces)
 &qupv3_id_0 {
@@ -609,6 +689,15 @@ &usb_2_hsphy {
 	status = "okay";
 };
 
+// children of i2c0 (QPS615_I2C)
+&i2c0 {
+	pcie_switch: qps615@77 {
+		compatible = "qcom,switch-i2c";
+		reg = <0x077>;
+		vdda-supply = <&vreg_qps615_rsex>;
+		status = "okay";
+	};
+};
 
 // children of i2c2 (I2C_PM)
 &i2c2 {
@@ -629,4 +718,26 @@ gpio_usb_hub_res {
 	};
 };
 
+// children of pcie1 (QPS615 switch)
+&pcie1 {
+	dummy-supply = <&pcie_switch>;
+	pcieport0: pcie@0 {
+		device_type = "pci";
+		reg = <0x0 0x0 0x0 0x0 0x0>;
+		#address-cells = <5>;
+		#size-cells = <0>;
+	};
+};
+
+// pin control
+&tlmm {
+	pcie1_reset_n: pcie1-reset-n-state {
+		pins = "gpio2";
+		function = "gpio";
+		drive-strength = <16>;
+		output-low;
+		bias-disable;
+	};
+};
+
 #endif