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Commit e229e9be authored by Nicola Sparnacci's avatar Nicola Sparnacci Committed by Michele Cirinei
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[SANTINO][PMIC] Configure PFUZE3000 over I2C1 

Added the needed changes to correctly enable the PMIC.

TODO: some Santino boards has PMIC supplying DDR with 1.5V instead of
the required 1.35V. Therefore, the PMIC should be programmed through
I2C to change reduce SW3 voltage. This should be done before RAM
initialization.
parent 6c3c0d0a
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1 merge request!145[SANTINO] Add support to Santino board
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arch/arm/dts/seco-imx6qdl-santino.dtsi
+ 34
− 70
View file @ e229e9be
......@@ -13,6 +13,7 @@
aliases {
mmc0 = &usdhc4;
mmc1 = &usdhc2;
i2c0 = &i2c1;
serial0 = &uart2;
};
......@@ -61,21 +62,19 @@
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
};
&i2c2 {
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze100@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
pmic: pfuze3000@8 {
compatible = "fsl,pfuze3000";
reg = <0x8>;
regulators {
sw1a_reg: sw1ab {
sw1a_reg: sw1a {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
......@@ -83,7 +82,7 @@
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
sw1b_reg: sw1b {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
......@@ -91,41 +90,32 @@
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
reg_SW4_3V3:sw2_reg: sw2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
sw3a_reg: sw3 {
// TODO: check if the voltage needs to be adjusted.
// Santino has 1.35V DDR3L but sometimes a PMIC
// starting with 1.5V is mounted on the board.
regulator-min-microvolt = <1345000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
regulator-boot-on;
regulator-always-on;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
......@@ -136,37 +126,18 @@
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
v33_reg: v33 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
vldo2_reg: vldo2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
regulator-boot-on;
};
};
};
......@@ -175,17 +146,10 @@
&iomuxc {
imx6qdl-seco-santino {
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c2_gpio: i2c2_gpio_grp {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0
MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
......@@ -249,11 +213,11 @@
};
&reg_pu {
vin-supply = <&sw1c_reg>;
vin-supply = <&sw1b_reg>;
};
&reg_soc {
vin-supply = <&sw1c_reg>;
vin-supply = <&sw1b_reg>;
};
&snvs_poweroff {
......
board/seco/imx6dl_santino/imx6dl_santino.c
+ 8
− 167
View file @ e229e9be
......@@ -175,14 +175,12 @@ void enable_lvds(struct display_info_t const *dev)
#ifdef CONFIG_SYS_I2C
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 12)
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
.gp = IMX_GPIO_NR(5, 26)
},
.sda = {
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 13)
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
.gp = IMX_GPIO_NR(5, 27)
}
};
#endif
......@@ -318,13 +316,12 @@ int board_mmc_getcd(struct mmc *mmc)
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
case USDHC4_BASE_ADDR:
ret = 1; /* eMMC/uSDHC4 is always present */
break;
}
return ret;
}
......@@ -349,7 +346,7 @@ int board_mmc_init( struct bd_info *bis ) {
index = 0;
break;
}
printf("%s: %d\n", __func__, __LINE__);
print_boot_device( );
imx_iomux_v3_setup_multiple_pads( usdhc_list_spl[index].pad,
......@@ -724,178 +721,22 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_POWER
int power_init_board(void)
{
struct pmic *pfuze;
unsigned int reg;
int ret;
pfuze = pfuze_common_init(I2C_PMIC);
if (!pfuze)
return -ENODEV;
if (is_mx6dqp())
ret = pfuze_mode_init(pfuze, APS_APS);
else
ret = pfuze_mode_init(pfuze, APS_PFM);
if (ret < 0)
return ret;
/* VGEN3 and VGEN5 corrected on i.mx6qp board */
if (!is_mx6dqp()) {
/* Increase VGEN3 from 2.5 to 2.8V */
pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, &reg);
reg &= ~LDO_VOL_MASK;
reg |= LDOB_2_80V;
pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg);
/* Increase VGEN5 from 2.8 to 3V */
pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &reg);
reg &= ~LDO_VOL_MASK;
reg |= LDOB_3_00V;
pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg);
}
if (is_mx6dqp()) {
/* set SW1C staby volatage 1.075V*/
pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
reg &= ~0x3f;
reg |= 0x1f;
pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
/* set SW2/VDDARM staby volatage 0.975V*/
pmic_reg_read(pfuze, PFUZE100_SW2STBY, &reg);
reg &= ~0x3f;
reg |= 0x17;
pmic_reg_write(pfuze, PFUZE100_SW2STBY, reg);
/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
pmic_reg_read(pfuze, PFUZE100_SW2CONF, &reg);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(pfuze, PFUZE100_SW2CONF, reg);
} else {
/* set SW1AB staby volatage 0.975V*/
pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);
reg &= ~0x3f;
reg |= 0x1b;
pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
/* set SW1C staby volatage 0.975V*/
pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
reg &= ~0x3f;
reg |= 0x1b;
pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
}
return 0;
}
#elif defined(CONFIG_DM_PMIC_PFUZE100)
int power_init_board(void)
{
struct udevice *dev;
unsigned int reg;
int ret;
dev = pfuze_common_init();
dev = pfuze3000_common_init();
if (!dev)
return -ENODEV;
if (is_mx6dqp())
ret = pfuze_mode_init(dev, APS_APS);
else
ret = pfuze_mode_init(dev, APS_PFM);
ret = pfuze_mode_init(dev, APS_APS);
if (ret < 0)
return ret;
/* VGEN3 and VGEN5 corrected on i.mx6qp board */
if (!is_mx6dqp()) {
/* Increase VGEN3 from 2.5 to 2.8V */
reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL);
reg &= ~LDO_VOL_MASK;
reg |= LDOB_2_80V;
pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg);
/* Increase VGEN5 from 2.8 to 3V */
reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
reg &= ~LDO_VOL_MASK;
reg |= LDOB_3_00V;
pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
}
if (is_mx6dqp()) {
/* set SW1C staby volatage 1.075V*/
reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
reg &= ~0x3f;
reg |= 0x1f;
pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
/* set SW2/VDDARM staby volatage 0.975V*/
reg = pmic_reg_read(dev, PFUZE100_SW2STBY);
reg &= ~0x3f;
reg |= 0x17;
pmic_reg_write(dev, PFUZE100_SW2STBY, reg);
/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
reg = pmic_reg_read(dev, PFUZE100_SW2CONF);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(dev, PFUZE100_SW2CONF, reg);
} else {
/* set SW1AB staby volatage 0.975V*/
reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
reg &= ~0x3f;
reg |= 0x1b;
pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
/* set SW1C staby volatage 0.975V*/
reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
reg &= ~0x3f;
reg |= 0x1b;
pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
}
return 0;
}
#endif
#ifdef CONFIG_LDO_BYPASS_CHECK
#ifdef CONFIG_POWER
......
configs/seco_imx6dl_santino_defconfig
+ 5
− 0
View file @ e229e9be
......@@ -102,7 +102,9 @@ CONFIG_PCI=y
CONFIG_CMD_PCI=y
# I2C
CONFIG_SYS_I2C=y
CONFIG_CMD_I2C=y
CONFIG_SYS_I2C_MXC=y
# SPI
CONFIG_SPI=y
......@@ -137,6 +139,7 @@ CONFIG_CMD_PING=y
# FDT
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="seco-imx6dl-santino"
CONFIG_OF_LIST="seco-imx6dl-santino"
CONFIG_DM_MMC=y
CONFIG_DM_I2C=y
CONFIG_DM_SPI=y
......@@ -149,6 +152,8 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_POWER_PFUZE3000=y
CONFIG_POWER_PFUZE100=y
CONFIG_DM_ETH=y
CONFIG_DM_PCI=y
CONFIG_PINCTRL=y
......
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