[SANTINO][DDR] Fix DDR table for 2x512MB

Setup the DDR table to access all the available RAM on Santino 2x512MB.

Signed-off-by: Nicola Sparnacci <nicola.sparnacci@seco.com>

board/seco/imx6dl_santino/ddr_config_2x512.h

@@ -48,7 +48,7 @@ __maybe_unused static int mx6solo_2x512_dcd_table[] = {
     /* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */
     0x021b001c, 0x05208030,  // MX6_MMDC_P0_MDSCR
     /* ZQ - Calibration */
-    0x021b0800, 0xa1390003,  // MX6_MMDC_P0_MPZQHWCTRL
+    0x021b0800, 0xA1390003,  // MX6_MMDC_P0_MPZQHWCTRL
     0x021b001c, 0x04008040,  // MX6_MMDC_P0_MDSCR
     0x021b0020, 0x00007800,  // MX6_MMDC_P0_MDREF
     0x021b0818, 0x00022227,  // MX6_MMDC_P0_MPODTCTRL
@@ -60,15 +60,15 @@ __maybe_unused static int mx6solo_2x512_dcd_table[] = {
 
 __maybe_unused static int mx6dl_2x512_dcd_table[] = {
     /* Write Leveling */
-    0x021b080c, 0x004C0057,  // MX6_MMDC_P0_MPWLDECTRL0
-    0x021b0810, 0x00240028,  // MX6_MMDC_P0_MPWLDECTRL1
+    0x021b080c, 0x00480050,  // MX6_MMDC_P0_MPWLDECTRL0
+    0x021b0810, 0x00240027,  // MX6_MMDC_P0_MPWLDECTRL1
     /* DQS gating, read delay, write delay calibration values */
-    0x021b083c, 0x423C0238,  // MX6_MMDC_P0_MPDGCTRL0
-    0x021b0840, 0x0214021C,  // MX6_MMDC_P0_MPDGCTRL1
+    0x021b083c, 0x4234022C,  // MX6_MMDC_P0_MPDGCTRL0
+    0x021b0840, 0x020C0214,  // MX6_MMDC_P0_MPDGCTRL1
     /* Read calibration */
-    0x021b0848, 0x42484A4A,  // MX6_MMDC_P0_MPRDDLCTL
-    /* write calibrttion */
-    0x021b0850, 0x3C38322E,  // MX6_MMDC_P0_MPWRDLCTL
+    0x021b0848, 0x44464A4A,  // MX6_MMDC_P0_MPRDDLCTL
+    /* write calibration */
+    0x021b0850, 0x3C36322E,  // MX6_MMDC_P0_MPWRDLCTL
     /* Complete calibration by forced measurement */
     0x021b08b8, 0x00000800,  // MX6_MMDC_P0_MPMUR0
     /* ========== MMDC init ========== */
@@ -83,9 +83,9 @@ __maybe_unused static int mx6dl_2x512_dcd_table[] = {
     0x021b002c, 0x000026D2,  // MX6_MMDC_P0_MDRWD
     0x021b0030, 0x00431023,  // MX6_MMDC_P0_MDOR
     /* CS0_END = 768MB (512 + 256)  in step da 256Mb -> [(2304*8/256) - 1] */
-    0x021b0040, 0x00000017,  // MX6_MMDC_P0_MDASP
+    0x021b0040, 0x00000027,  // MX6_MMDC_P0_MDASP
     /* SDE_1=0; ROW=3; BL=1; DSIZ=1 -> 32 bit */
-    0x021b0000, 0x83190000,  // MX6_MMDC_P0_MDCTL
+    0x021b0000, 0x84190000,  // MX6_MMDC_P0_MDCTL
     /* Initialize DDR3 on CS_0 */
     0x021b001c, 0x02008032,  // MX6_MMDC_P0_MDSCR
     0x021b001c, 0x00008033,  // MX6_MMDC_P0_MDSCR