[i.MX8M] [C25] add C25 board based on 4.x version

Added initial version.

	modified:   arch/arm/dts/Makefile
	new file:   arch/arm/dts/seco-imx8mq-c25.dts
	modified:   arch/arm/mach-imx/imx8m/Kconfig
	modified:   board/seco/common/proto_seco.h
	new file:   board/seco/imx8mq_c25/Kconfig
	new file:   board/seco/imx8mq_c25/MAINTAINERS
	new file:   board/seco/imx8mq_c25/Makefile
	new file:   board/seco/imx8mq_c25/ddr/ddr.h
	new file:   board/seco/imx8mq_c25/ddr/ddr4/ddr_init.c
	new file:   board/seco/imx8mq_c25/ddr/ddr4/ddrphy_train.c
	new file:   board/seco/imx8mq_c25/ddr/helper.c
	new file:   board/seco/imx8mq_c25/ddr/wait_ddrphy_training_complete.c
	new file:   board/seco/imx8mq_c25/env_conf.h
	new file:   board/seco/imx8mq_c25/imx8mq_c25.c
	new file:   board/seco/imx8mq_c25/spl.c
	new file:   board/seco/imx8mq_c25/strap_cfg.c
	new file:   board/seco/imx8mq_c25/strap_cfg.h
	new file:   configs/seco_imx8mq_c25_defconfig
	new file:   include/configs/seco_imx8mq_c25.h
	modified:   include/configs/seco_mx8_dtbo.h
	modified:   include/seco/seco_env_gd.h

Signed-off-by: Mikhail Vanyulin <mikhail.vanyulin@rtsoft.de>

arch/arm/dts/Makefile

@@ -904,6 +904,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	seco-imx8mn-c72.dtb \
 	seco-imx8mm-c72.dtb \
 	seco-imx8mq-c20.dtb \
+	seco-imx8mq-c25.dtb \
 	seco-imx8mq-c12.dtb \
 	seco-imx8mm-c61.dtb 
 

arch/arm/dts/seco-imx8mq-c25.dts

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 SECO
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+#include "dt-bindings/net/ti-dp83867.h"
+
+/ {
+	model = "SECO i.MX8MQ C25";
+	compatible = "fsl,imx8mq-evk", "seco,imx8mq-c25", "fsl,imx8mq";
+
+	chosen {
+		bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
+		stdout-path = &uart1;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "VSD_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+			off-on-delay-us = <20000>;
+			enable-active-high;
+		};
+	};
+
+	modem_reset: modem-reset {
+		compatible = "gpio-reset";
+		reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <2000>;
+		reset-post-delay-ms = <40>;
+		#reset-cells = <0>;
+	};
+
+	wm8524: audio-codec {
+		#sound-dai-cells = <0>;
+		compatible = "wlf,wm8524";
+		wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		ledpwm2 {
+			label = "PWM2";
+			pwms = <&pwm2 0 50000>;
+			max-brightness = <255>;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	seco-imx8mq-c25 {
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
+				MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
+				MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
+				MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
+				MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
+				MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
+				MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
+				MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
+				MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
+				MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
+				MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
+				MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
+				MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+				MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+				/* ENET RESET */
+				MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3		0x19
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
+				MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
+				MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
+			>;
+		};
+
+		pinctrl_i2c1_gpio: i2c1grp-gpio {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14		0x7f
+				MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15		0x7f
+			>;
+		};
+
+		pinctrl_i2c2_gpio: i2c2grp-gpio {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16		0x7f
+				MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17		0x7f
+			>;
+		};
+
+		pinctrl_pwm2: pwm2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT		0x16
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x79
+				MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x79
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
+				MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+			>;
+		};
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@9 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <9>;
+			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze100@8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x8>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3ab {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+	status = "disabled";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	status = "okay";
+};
+
+&uart1 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
+	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	usb-role-switch;
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+	status = "okay";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};

arch/arm/mach-imx/imx8m/Kconfig

@@ -80,6 +80,10 @@ config TARGET_SECO_IMX8MQ_C20
 	bool "seco_imx8mq_c20"
 	select IMX8MQ
 
+config TARGET_SECO_IMX8MQ_C25
+	bool "seco_imx8mq_c25"
+	select IMX8MQ
+
 config TARGET_SECO_IMX8MQ_C12
 	bool "seco_imx8mq_c12"
 	select IMX8MQ 
@@ -315,6 +319,7 @@ source "board/phytec/phycore_imx8mm/Kconfig"
 source "board/phytec/phycore_imx8mp/Kconfig"
 source "board/seco/imx8mp_d18/Kconfig"
 source "board/seco/imx8mq_c20/Kconfig"
+source "board/seco/imx8mq_c25/Kconfig"
 source "board/seco/imx8mq_c12/Kconfig"
 source "board/seco/imx8m_c72/Kconfig"
 source "board/seco/imx8mm_c61/Kconfig"

board/seco/common/proto_seco.h

@@ -46,10 +46,16 @@ extern int usdhc_devno[4];
 #if defined CONFIG_TARGET_SECO_IMX8MP_D18
 extern int usdhc_devno[3];
 #endif
-#if defined CONFIG_TARGET_SECO_IMX8MQ_C20 || defined CONFIG_TARGET_SECO_IMX8MQ_C12 || defined CONFIG_TARGET_SECO_IMX8QXP_C57
+#if defined CONFIG_TARGET_SECO_IMX8MQ_C20 || \
+	defined CONFIG_TARGET_SECO_IMX8MQ_C12 || \
+	defined CONFIG_TARGET_SECO_IMX8QXP_C57 || \
+	defined CONFIG_TARGET_SECO_IMX8MQ_C25
 extern int usdhc_devno[2];
 #endif
-#if defined CONFIG_TARGET_SECO_IMX8MP_D18 || CONFIG_TARGET_SECO_IMX8MQ_C20 || defined CONFIG_TARGET_SECO_IMX8MQ_C12
+#if defined CONFIG_TARGET_SECO_IMX8MP_D18 || \
+	defined CONFIG_TARGET_SECO_IMX8MQ_C20 || \
+	defined CONFIG_TARGET_SECO_IMX8MQ_C12 || \
+	defined CONFIG_TARGET_SECO_IMX8MQ_C25
 extern int print_bootinfo(void);
 #endif
 __weak void autoset_boot_device(void);

board/seco/imx8mq_c25/Kconfig

+if TARGET_SECO_IMX8MQ_C25
+
+config SYS_BOARD
+	default "imx8mq_c25"
+
+config SYS_VENDOR
+	default "seco"
+
+config SYS_CONFIG_NAME
+	default "seco_imx8mq_c25"
+
+source "board/seco/common/Kconfig"
+
+endif

board/seco/imx8mq_c25/MAINTAINERS

+TARGET_SECO_IMX8MQ_C25
+M:	Michele Cirinei <michele.cirinei@seco.com>
+S:	Maintained
+F:	board/seco/imx8mq_c25/env_conf.h
+F:	board/seco/imx8mq_c25/imx8mq_c25.c
+F:	board/seco/imx8mq_c25/Kconfig
+F:	board/seco/imx8mq_c25/MAINTAINERS
+F:	board/seco/imx8mq_c25/Makefile
+F:	board/seco/imx8mq_c25/spl.c
+F:	board/seco/imx8mq_c25/strap_cfg.c
+F:	board/seco/imx8mq_c25/strap_cfg.h
+F:	board/seco/imx8mq_c25/ddr/ddr.h
+F:	board/seco/imx8mq_c25/ddr/helper.c
+F:	board/seco/imx8mq_c25/ddr/wait_ddrphy_training_complete.c
+F:	board/seco/imx8mq_c25/ddr/ddr4/ddr_init.c
+F:	board/seco/imx8mq_c25/ddr/ddr4/ddrphy_train.c
+F:	configs/seco_imx8mq_c25_defconfig
+F:	include/configs/seco_imx8mq_c25.h
+F:	arc/arm/dts/seco-imx8mq-c25.dts

board/seco/imx8mq_c25/Makefile

+#
+# Copyright 2024 SECO
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mq_c25.o strap_cfg.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += ddr/helper.o
+obj-y += ddr/ddr4/ddr_init.o ddr/ddr4/ddrphy_train.o
+endif

board/seco/imx8mq_c25/ddr/ddr.h

+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 SECO
+ */
+
+#ifndef SRC_DDRC_RCR_ADDR
+#define SRC_DDRC_RCR_ADDR (SRC_IPS_BASE_ADDR + 0x1000)
+#endif
+#ifndef DDR_CSD1_BASE_ADDR
+#define DDR_CSD1_BASE_ADDR 0x40000000
+#endif
+
+void ddr_load_train_code(enum fw_type type);
+int wait_ddrphy_training_complete(void);
+void ddr4_phyinit_train_2400mts(void);

board/seco/imx8mq_c25/ddr/ddr4/ddr_init.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2017.03_4.9.51_imx8m_ga
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/clock.h>
+#include "../ddr.h"
+#include "../../strap_cfg.h"
+
+
+#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
+#define ddr_printf(args...) printf(args)
+#else
+#define ddr_printf(args...)
+#endif
+
+#include "../wait_ddrphy_training_complete.c"
+#ifndef SRC_DDRC_RCR_ADDR
+#define SRC_DDRC_RCR_ADDR (SRC_IPS_BASE_ADDR + 0x1000)
+#endif
+#ifndef DDR_CSD1_BASE_ADDR
+#define DDR_CSD1_BASE_ADDR 0x40000000
+#endif
+#define SILICON_TRAIN
+
+int ddr_cfg_phy(struct dram_timing_info *timing_info);
+volatile unsigned int tmp, tmp_t, i;
+int ddr_init(struct dram_timing_info *timing_info)
+{
+	/** Initialize DDR clock and DDRC registers **/
+	reg32_write(0x30330234, 0x0);
+	reg32_write(0x30330238, 0x0);
+	reg32_write(0x3033049c, 0xe);
+	reg32_write(0x303304a0, 0xe);
+	reg32_write(0x303304f4, 0x0);
+	reg32_write(0x3038a088, 0x7070000);
+	reg32_write(0x3038a084, 0x4030000);
+	reg32_write(0x303a00ec, 0xffff);
+	tmp = reg32_read(0x303a00f8);
+	tmp |= 0x20;
+	reg32_write(0x303a00f8, tmp);
+	reg32_write(0x30391000, 0x8f000000);
+	reg32_write(0x30391004, 0x8f000000);
+	reg32_write(0x30360068, 0xec6480);
+	tmp = reg32_read(0x30360060);
+	tmp &= ~0x80;
+	reg32_write(0x30360060, tmp);
+	tmp = reg32_read(0x30360060);
+	tmp |= 0x200;
+	reg32_write(0x30360060, tmp);
+	tmp = reg32_read(0x30360060);
+	tmp &= ~0x20;
+	reg32_write(0x30360060, tmp);
+	tmp = reg32_read(0x30360060);
+	tmp &= ~0x10;
+	reg32_write(0x30360060, tmp);
+	do {
+		tmp = reg32_read(0x30360060);
+		if (tmp&0x80000000)
+			break;
+	} while (1);
+	reg32_write(0x30391000, 0x8f000006);
+	reg32_write(0x3d400304, 0x1);
+	reg32_write(0x3d400030, 0x1);
+	if (C25_IS_1GB)
+		reg32_write(0x3d400000, 0x81040010);
+	if (C25_IS_2GB || C25_IS_4GB)
+		reg32_write(0x3d400000, 0x83040010);
+	reg32_write(0x3d400028, 0x1);
+	reg32_write(0x3d400030, 0xaa);
+	reg32_write(0x3d400034, 0x221306);
+	reg32_write(0x3d400038, 0x840000);
+	reg32_write(0x3d40003c, 0x30);
+	reg32_write(0x3d400050, 0x210070);
+	reg32_write(0x3d400054, 0x10008);
+	reg32_write(0x3d400060, 0x10);
+	if (C25_IS_2GB || C25_IS_1GB)
+		reg32_write(0x3d400064, 0x490060);
+	if (C25_IS_4GB)
+		reg32_write(0x3d400064, 0x49009c);
+	reg32_write(0x3d4000c0, 0x0);
+	reg32_write(0x3d4000c4, 0x1000);
+	reg32_write(0x3d4000d0, 0xc0030126);
+	reg32_write(0x3d4000d4, 0x770000);
+	reg32_write(0x3d4000dc, 0x8340001);
+	reg32_write(0x3d4000e0, 0x180240);
+	reg32_write(0x3d4000e4, 0x110000);
+	reg32_write(0x3d4000e8, 0x2000640);
+	reg32_write(0x3d4000ec, 0x816);
+	reg32_write(0x3d4000f0, 0x22);
+	reg32_write(0x3d4000f4, 0x527);
+	reg32_write(0x3d400100, 0x11122914);
+	reg32_write(0x3d400104, 0x4051c);
+	reg32_write(0x3d400108, 0x608050d);
+	reg32_write(0x3d40010c, 0x400c);
+	reg32_write(0x3d400110, 0x8030409);
+	reg32_write(0x3d400114, 0x6060403);
+	reg32_write(0x3d40011c, 0x606);
+	if (C25_IS_2GB || C25_IS_1GB)
+		reg32_write(0x3d400120, 0x4040d07);
+	if (C25_IS_4GB)
+		reg32_write(0x3d400120, 0x5050d08);
+	reg32_write(0x3d400124, 0x2040a);
+	if (C25_IS_2GB || C25_IS_1GB)
+		reg32_write(0x3d40012c, 0x1309010e);
+	if (C25_IS_4GB)
+		reg32_write(0x3d40012c, 0x1409010e);
+	reg32_write(0x3d400130, 0x8);
+	reg32_write(0x3d40013c, 0x0);
+	reg32_write(0x3d400180, 0x1000040);
+	reg32_write(0x3d400184, 0x493e);
+	reg32_write(0x3d400190, 0x38b8207);
+	reg32_write(0x3d400194, 0x2020303);
+	reg32_write(0x3d400198, 0x7f04011);
+	reg32_write(0x3d40019c, 0xb0);
+	reg32_write(0x3d4001a0, 0xe0400018);
+	reg32_write(0x3d4001a4, 0x48005a);
+	reg32_write(0x3d4001a8, 0x80000000);
+	reg32_write(0x3d4001b0, 0x1);
+	reg32_write(0x3d4001b4, 0xb07);
+	reg32_write(0x3d4001b8, 0x4);
+	reg32_write(0x3d4001c0, 0x1);
+	reg32_write(0x3d4001c4, 0x0);
+	if (C25_IS_1GB)
+		reg32_write(0x3d400200, 0x3f1f);
+	if (C25_IS_2GB)
+		reg32_write(0x3d400200, 0x3f16);
+	if (C25_IS_4GB)
+		reg32_write(0x3d400200, 0x3f17);
+	reg32_write(0x3d400204, 0x3f0909);
+	reg32_write(0x3d400208, 0x1010100);
+	reg32_write(0x3d40020c, 0x1010101);
+	reg32_write(0x3d400210, 0x1f1f);
+	reg32_write(0x3d400214, 0x7070707);
+	if (C25_IS_2GB || C25_IS_1GB)
+		reg32_write(0x3d400218, 0xf070707);
+	if (C25_IS_4GB)
+		reg32_write(0x3d400218, 0x7070707);
+	reg32_write(0x3d40021c, 0xf0f);
+	reg32_write(0x3d400220, 0x3f01);
+	reg32_write(0x3d400240, 0x6000610);
+	reg32_write(0x3d400244, 0x1323);
+	reg32_write(0x3d400250, 0x317d1a07);
+	reg32_write(0x3d400254, 0xf);
+	reg32_write(0x3d40025c, 0x2a001b76);
+	reg32_write(0x3d400264, 0x9);
+	reg32_write(0x3d40026c, 0x30000e06);
+	reg32_write(0x3d400300, 0x14);
+	reg32_write(0x3d400304, 0x0);
+	reg32_write(0x3d40030c, 0x0);
+	reg32_write(0x3d400320, 0x1);
+	reg32_write(0x3d40036c, 0x10);
+	reg32_write(0x3d400400, 0x11);
+	reg32_write(0x3d400404, 0x13193);
+	reg32_write(0x3d400408, 0x6096);
+	reg32_write(0x3d400490, 0x1);
+	reg32_write(0x3d400494, 0x2000c00);
+	reg32_write(0x3d400498, 0x3c00db);
+	reg32_write(0x3d40049c, 0x100001);
+	reg32_write(0x3d4004a0, 0x41f);
+	reg32_write(0x3d402050, 0x210070);
+	if (C25_IS_2GB || C25_IS_1GB)
+		reg32_write(0x3d402064, 0x300040);
+	if (C25_IS_4GB)
+		reg32_write(0x3d402064, 0x300068);
+	reg32_write(0x3d4020dc, 0x2100001);
+	reg32_write(0x3d4020e0, 0x40);
+	reg32_write(0x3d4020e8, 0x2000640);
+	reg32_write(0x3d4020ec, 0x416);
+	reg32_write(0x3d402100, 0xd0c1b0d);
+	reg32_write(0x3d402104, 0x30313);
+	reg32_write(0x3d402108, 0x506040a);
+	reg32_write(0x3d40210c, 0x400c);
+	reg32_write(0x3d402110, 0x6030306);
+	reg32_write(0x3d402114, 0x4040302);
+	reg32_write(0x3d40211c, 0x404);
+	if (C25_IS_2GB || C25_IS_1GB)
+		reg32_write(0x3d402120, 0x3030d05);
+	if (C25_IS_4GB)
+		reg32_write(0x3d402120, 0x4040d06);
+	reg32_write(0x3d402124, 0x20308);
+	if (C25_IS_2GB || C25_IS_1GB)
+		reg32_write(0x3d40212c, 0x1106010e);
+	if (C25_IS_4GB)
+		reg32_write(0x3d40212c, 0x1206010e);
+	reg32_write(0x3d402130, 0x8);
+	reg32_write(0x3d40213c, 0x0);
+	reg32_write(0x3d402180, 0x1000040);
+	reg32_write(0x3d402190, 0x3868204);
+	reg32_write(0x3d402194, 0x2020303);
+	reg32_write(0x3d4021b4, 0x604);
+	reg32_write(0x3d4021b8, 0x4);
+	reg32_write(0x3d402240, 0x6000608);
+	reg32_write(0x3d403050, 0x210070);
+	if (C25_IS_2GB || C25_IS_1GB)
+		reg32_write(0x3d403064, 0x20002a);
+	if (C25_IS_4GB)
+		reg32_write(0x3d403064, 0x200045);
+	reg32_write(0x3d4030dc, 0x1);
+	reg32_write(0x3d4030e0, 0x40);
+	reg32_write(0x3d4030e8, 0x2000640);
+	reg32_write(0x3d4030ec, 0x16);
+	reg32_write(0x3d403100, 0xb081209);
+	reg32_write(0x3d403104, 0x2020d);
+	reg32_write(0x3d403108, 0x5050309);
+	reg32_write(0x3d40310c, 0x400c);
+	reg32_write(0x3d403110, 0x4030205);
+	reg32_write(0x3d403114, 0x3030202);
+	reg32_write(0x3d40311c, 0x303);
+	if (C25_IS_2GB || C25_IS_1GB)
+		reg32_write(0x3d403120, 0x2030d04);
+	if (C25_IS_4GB)
+		reg32_write(0x3d403120, 0x3040d04);
+	reg32_write(0x3d403124, 0x20208);
+	reg32_write(0x3d40312c, 0x1005010e);
+	reg32_write(0x3d403130, 0x8);
+	reg32_write(0x3d40313c, 0x0);
+	reg32_write(0x3d403180, 0x1000040);
+	reg32_write(0x3d403190, 0x3848204);
+	reg32_write(0x3d403194, 0x2020303);
+	reg32_write(0x3d4031b4, 0x404);
+	reg32_write(0x3d4031b8, 0x4);
+	reg32_write(0x3d403240, 0x6000600);
+	reg32_write(0x3d400060, 0x11);
+	reg32_write(0x30391000, 0x8f000004);
+	reg32_write(0x30391000, 0x8f000000);
+	reg32_write(0x3d400304, 0x0);
+	reg32_write(0x3d400030, 0xaa);
+	reg32_write(0x3d400320, 0x0);
+	reg32_write(0x3d4001b0, 0x0);
+
+	/* Configure DDR PHY's registers */
+	ddr_cfg_phy(NULL);
+
+	reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+	reg32_write(DDRC_SWCTL(0), 0x0000);
+	/*
+	 * ------------------- 9 -------------------
+	 * Set DFIMISC.dfi_init_start to 1
+	 *  -----------------------------------------
+	 */
+	reg32_write(DDRC_DFIMISC(0), 0x00000030);
+	reg32_write(DDRC_SWCTL(0), 0x0001);
+
+	/* wait DFISTAT.dfi_init_complete to 1 */
+	tmp_t = 0;
+	while (tmp_t == 0) {
+		tmp  = reg32_read(DDRC_DFISTAT(0));
+		tmp_t = tmp & 0x01;
+		tmp  = reg32_read(DDRC_MRSTAT(0));
+	}
+
+	reg32_write(DDRC_SWCTL(0), 0x0000);
+
+	/* clear DFIMISC.dfi_init_complete_en */
+	reg32_write(DDRC_DFIMISC(0), 0x00000010);
+	reg32_write(DDRC_DFIMISC(0), 0x00000011);
+	reg32_write(DDRC_PWRCTL(0), 0x00000088);
+
+	tmp = reg32_read(DDRC_CRCPARSTAT(0));
+	/*
+	 * set SWCTL.sw_done to enable quasi-dynamic register
+	 * programming outside reset.
+	 */
+	reg32_write(DDRC_SWCTL(0), 0x00000001);
+
+	/* wait SWSTAT.sw_done_ack to 1 */
+	while ((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
+		;
+
+	/* wait STAT.operating_mode([1:0] for ddr3) to normal state */
+	while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1)
+		;
+
+	reg32_write(DDRC_PWRCTL(0), 0x00000088);
+	/* reg32_write(DDRC_PWRCTL(0), 0x018a); */
+	tmp = reg32_read(DDRC_CRCPARSTAT(0));
+
+	/* enable port 0 */
+	reg32_write(DDRC_PCTRL_0(0), 0x00000001);
+	/* enable DDR auto-refresh mode */
+	tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1;
+	reg32_write(DDRC_RFSHCTL3(0), tmp);
+
+	return 0;
+}

board/seco/imx8mq_c25/ddr/helper.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 NXP
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/sections.h>
+
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMEM_LEN 32768
+#define DMEM_LEN 16384
+#define IMEM_2D_OFFSET	49152
+
+#define IMEM_OFFSET_ADDR 0x00050000
+#define DMEM_OFFSET_ADDR 0x00054000
+#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
+
+/* We need PHY iMEM PHY is 32KB padded */
+void ddr_load_train_code(enum fw_type type)
+{
+	u32 tmp32, i;
+	u32 error = 0;
+	unsigned long pr_to32, pr_from32;
+	unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
+	unsigned long imem_start = (unsigned long)&_end + fw_offset;
+	unsigned long dmem_start = imem_start + IMEM_LEN;
+
+	pr_from32 = imem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+	for (i = 0x0; i < IMEM_LEN; ) {
+		tmp32 = readl(pr_from32);
+		writew(tmp32 & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		pr_from32 += 4;
+		i += 4;
+	}
+
+	pr_from32 = dmem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+	for (i = 0x0; i < DMEM_LEN;) {
+		tmp32 = readl(pr_from32);
+		writew(tmp32 & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		pr_from32 += 4;
+		i += 4;
+	}
+
+	printf("check ddr_imem code\n");
+	pr_from32 = imem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+	for (i = 0x0; i < IMEM_LEN;) {
+		tmp32 = (readw(pr_to32) & 0x0000ffff);
+		pr_to32 += 4;
+		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+
+		if (tmp32 != readl(pr_from32)) {
+			printf("%lx %lx\n", pr_from32, pr_to32);
+			error++;
+		}
+		pr_from32 += 4;
+		pr_to32 += 4;
+		i += 4;
+	}
+	if (error)
+		printf("check ddr_imem code fail=%d\n", error);
+	else
+		printf("check ddr_imem code pass\n");
+
+	printf("check ddr_dmem code\n");
+	pr_from32 = dmem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+	for (i = 0x0; i < DMEM_LEN;) {
+		tmp32 = (readw(pr_to32) & 0x0000ffff);
+		pr_to32 += 4;
+		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+		if (tmp32 != readl(pr_from32)) {
+			printf("%lx %lx\n", pr_from32, pr_to32);
+			error++;
+		}
+		pr_from32 += 4;
+		pr_to32 += 4;
+		i += 4;
+	}
+
+	if (error)
+		printf("check ddr_dmem code fail=%d", error);
+	else
+		printf("check ddr_dmem code pass\n");
+}

board/seco/imx8mq_c25/ddr/wait_ddrphy_training_complete.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 NXP
+ */
+
+static inline void poll_pmu_message_ready(void)
+{
+	unsigned int reg;
+
+	do {
+		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
+	} while (reg & 0x1);
+}
+
+static inline void ack_pmu_message_recieve(void)
+{
+	unsigned int reg;
+
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031, 0x0);
+
+	do {
+		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
+	} while (!(reg & 0x1));
+
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031, 0x1);
+}
+
+static inline unsigned int get_mail(void)
+{
+	unsigned int reg;
+
+	poll_pmu_message_ready();
+
+	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
+
+	ack_pmu_message_recieve();
+
+	return reg;
+}
+
+static inline unsigned int get_stream_message(void)
+{
+	unsigned int reg, reg2;
+
+	poll_pmu_message_ready();
+
+	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
+
+	reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034);
+
+	reg2 = (reg2 << 16) | reg;
+
+	ack_pmu_message_recieve();
+
+	return reg2;
+}
+
+static inline void decode_major_message(unsigned int mail)
+{
+	ddr_printf("[PMU Major message = 0x%08x]\n", mail);
+}
+
+static inline void decode_streaming_message(void)
+{
+	unsigned int string_index, arg __maybe_unused;
+	int i = 0;
+
+	string_index = get_stream_message();
+	ddr_printf("	PMU String index = 0x%08x\n", string_index);
+	while (i < (string_index & 0xffff)) {
+		arg = get_stream_message();
+		ddr_printf("	arg[%d] = 0x%08x\n", i, arg);
+		i++;
+	}
+
+	ddr_printf("\n");
+}
+
+int wait_ddrphy_training_complete(void)
+{
+	unsigned int mail;
+
+	while (1) {
+		mail = get_mail();
+		decode_major_message(mail);
+		if (mail == 0x08) {
+			decode_streaming_message();
+		} else if (mail == 0x07) {
+			printf("Training PASS\n");
+			return 0;
+		} else if (mail == 0xff) {
+			printf("Training FAILED\n");
+			return -1;
+		}
+	}
+}

board/seco/imx8mq_c25/env_conf.h

+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2024 Seco
+ *
+ * Author: Davide Cardillo <davide.cardillo@seco.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+
+
+#include <seco/env_common.h>
+#include <configs/seco_mx8_dtbo.h>
+
+
+#define STR_HELPER(x) #x
+#define STR(x) STR_HELPER(x)
+
+
+/* *********************************** IMX8 *********************************** */
+
+data_boot_dev_t kern_dev_imx8_list[] = {
+	{ SECO_DEV_TYPE_EMMC,     SECO_DEV_LABEL_EMMC,   STR(MACRO_ENV_KERNEL_SRC_USDHCI),   SCFG_BOOT_DEV_ID_EMMC,    LOAD_ADDR_KERNEL_LOCAL_DEV,  SCFG_KERNEL_FILENAME },
+	{ SECO_DEV_TYPE_SD,       SECO_DEV_LABEL_SD,     STR(MACRO_ENV_KERNEL_SRC_USDHCI),   SCFG_BOOT_DEV_ID_SD,      LOAD_ADDR_KERNEL_LOCAL_DEV,  SCFG_KERNEL_FILENAME },
+	{ SECO_DEV_TYPE_USB,      SECO_DEV_LABEL_USB,    STR(MACRO_ENV_KERNEL_SRC_USB),      SCFG_BOOT_DEV_ID_USB,     LOAD_ADDR_KERNEL_LOCAL_DEV,  SCFG_KERNEL_FILENAME },
+	{ SECO_DEV_TYPE_TFTP,     SECO_DEV_LABEL_TFTP,   STR(MACRO_ENV_KERNEL_SRC_TFTP),     "",                       LOAD_ADDR_KERNEL_REMOTE_DEV, SCFG_KERNEL_FILENAME },
+};
+
+size_t kern_dev_imx8_size = ARRAY_SIZE(kern_dev_imx8_list);
+
+
+data_boot_dev_t fdt_dev_imx8_list[] = {
+	{ SECO_DEV_TYPE_EMMC,     SECO_DEV_LABEL_EMMC,   STR(MACRO_ENV_FDT_SRC_USDHCI),   SCFG_BOOT_DEV_ID_EMMC,    LOAD_ADDR_FDT_LOCAL_DEV,  SCFG_DEFAULT_FDT_IMX8_FILE },
+	{ SECO_DEV_TYPE_SD,       SECO_DEV_LABEL_SD,     STR(MACRO_ENV_FDT_SRC_USDHCI),   SCFG_BOOT_DEV_ID_SD,      LOAD_ADDR_FDT_LOCAL_DEV,  SCFG_DEFAULT_FDT_IMX8_FILE },
+	{ SECO_DEV_TYPE_USB,      SECO_DEV_LABEL_USB,    STR(MACRO_ENV_FDT_SRC_USB),      SCFG_BOOT_DEV_ID_USB,     LOAD_ADDR_FDT_LOCAL_DEV,  SCFG_DEFAULT_FDT_IMX8_FILE },
+	{ SECO_DEV_TYPE_TFTP,     SECO_DEV_LABEL_TFTP,   STR(MACRO_ENV_FDT_SRC_TFTP),     "",                       LOAD_ADDR_FDT_REMOTE_DEV, SCFG_DEFAULT_FDT_IMX8_FILE },
+};
+
+size_t fdt_dev_imx8_size = ARRAY_SIZE(fdt_dev_imx8_list);
+
+
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+data_boot_dev_t fdt_overlay_dev_imx8_list[] = {
+	{ SECO_DEV_TYPE_EMMC,     SECO_DEV_LABEL_EMMC,   STR(MACRO_ENV_FDT_OVERLAY_SRC_USDHCI),   SCFG_BOOT_DEV_ID_EMMC,    "", "" },
+	{ SECO_DEV_TYPE_SD,       SECO_DEV_LABEL_SD,     STR(MACRO_ENV_FDT_OVERLAY_SRC_USDHCI),   SCFG_BOOT_DEV_ID_SD,      "", "" },
+	{ SECO_DEV_TYPE_USB,      SECO_DEV_LABEL_USB,    STR(MACRO_ENV_FDT_OVERLAY_SRC_USB),      SCFG_BOOT_DEV_ID_USB,     "", "" },
+	{ SECO_DEV_TYPE_TFTP,     SECO_DEV_LABEL_TFTP,   STR(MACRO_ENV_FDT_OVERLAY_SRC_TFTP),     "",                       "", "" },
+};
+
+size_t fdt_overlay_dev_imx8_size = ARRAY_SIZE(fdt_overlay_dev_imx8_list);
+#endif  /* CONFIG_OF_LIBFDT_OVERLAY */
+
+
+data_boot_dev_t ramfs_dev_imx8_list[] = {
+	{ SECO_DEV_TYPE_NONE,     SECO_DEV_LABEL_NONE,   "0x0",                             "0",                      LOAD_ADDR_RAMFS_LOCAL_DEV,    ""                  },
+	{ SECO_DEV_TYPE_EMMC,     SECO_DEV_LABEL_EMMC,   STR(MACRO_ENV_RAMFS_SRC_USDHCI),   SCFG_BOOT_DEV_ID_EMMC,    LOAD_ADDR_RAMFS_LOCAL_DEV,    SCFG_RAMFS_FILENAME },
+	{ SECO_DEV_TYPE_SD,       SECO_DEV_LABEL_SD,     STR(MACRO_ENV_RAMFS_SRC_USDHCI),   SCFG_BOOT_DEV_ID_SD,      LOAD_ADDR_RAMFS_LOCAL_DEV,    SCFG_RAMFS_FILENAME },
+	{ SECO_DEV_TYPE_USB,      SECO_DEV_LABEL_USB,    STR(MACRO_ENV_RAMFS_SRC_USB),      SCFG_BOOT_DEV_ID_USB,     LOAD_ADDR_RAMFS_LOCAL_DEV,    SCFG_RAMFS_FILENAME },
+	{ SECO_DEV_TYPE_TFTP,     SECO_DEV_LABEL_TFTP,   STR(MACRO_ENV_RAMFS_SRC_TFTP),     "",                       LOAD_ADDR_RAMFS_REMOTE_DEV,   SCFG_RAMFS_FILENAME },
+};
+
+size_t ramfs_dev_imx8_size = ARRAY_SIZE(ramfs_dev_imx8_list);
+
+
+data_boot_dev_t filesystem_dev_imx8_list[] = {
+	{ SECO_DEV_TYPE_EMMC,     SECO_DEV_LABEL_EMMC,   STR(MACRO_ENV_FS_SRC_USDHCI),   SCFG_ROOT_DEV_ID_EMMC,    "", "" },
+	{ SECO_DEV_TYPE_SD,       SECO_DEV_LABEL_SD,     STR(MACRO_ENV_FS_SRC_USDHCI),   SCFG_ROOT_DEV_ID_SD,      "", "" },
+	{ SECO_DEV_TYPE_USB,      SECO_DEV_LABEL_USB,    STR(MACRO_ENV_FS_SRC_USB),      SCFG_ROOT_DEV_ID_USB,     "", "" },
+	{ SECO_DEV_TYPE_NFS,      SECO_DEV_LABEL_NFS,    STR(MACRO_ENV_FS_SRC_NFS),      "",                       "", "" },
+};
+
+size_t filesystem_dev_imx8_size = ARRAY_SIZE(filesystem_dev_imx8_list);
+
+
+
+/* LVDSx2, HDMI, eDP */
+video_mode_t video_mode_list_CFG_0[] = {
+	{
+		/* NO DISPLAY */
+		.label    = SECO_VIDEO_LABEL_NONE,
+		.video = {
+			{ VIDEO_NOT_USED, NO_VIDEO, NO_VIDEO_ARGS },
+		},
+		.panel_name = "none",
+		.dtbo_conf_file = NULL,
+		.use_bootargs = 0,
+	}, {
+		/* LVDS */
+		.label    = SECO_VIDEO_LABEL_LVDSx2,
+		.video = {
+			{ VIDEO_USED, VIDEO_LVDSx2, NO_VIDEO_ARGS },
+		},
+		.panel_name = "none",
+		.dtbo_conf_file = STR(ENV_DTBO_C25_LVDS_DUAL),
+		.use_bootargs = 0,
+	}, {
+		/* HDMI */
+		.label    = SECO_VIDEO_LABEL_HDMI,
+		.video = {
+			{ VIDEO_USED, VIDEO_HDMI, NO_VIDEO_ARGS },
+		},
+		.panel_name = "none",
+		.dtbo_conf_file = STR(ENV_DTBO_C25_HDMI),
+		.use_bootargs = 0,
+	}, {
+		/* eDP */
+		.label    = SECO_VIDEO_LABEL_EDP,
+		.video = {
+			{ VIDEO_USED, VIDEO_EDP, NO_VIDEO_ARGS },
+		},
+		.panel_name = "none",
+		.dtbo_conf_file = STR(ENV_DTBO_C25_EDP),
+		.use_bootargs = 0,
+	},
+};
+
+size_t video_mode_size_CFG_0 = ARRAY_SIZE(video_mode_list_CFG_0);
+
+
+/* LVDSx2, DP, eDP */
+video_mode_t video_mode_list_CFG_1[] = {
+	{
+		/* NO DISPLAY */
+		.label    = SECO_VIDEO_LABEL_NONE,
+		.video = {
+			{ VIDEO_NOT_USED, NO_VIDEO, NO_VIDEO_ARGS },
+		},
+		.panel_name = "none",
+		.dtbo_conf_file = NULL,
+		.use_bootargs = 0,
+	}, {
+		/* LVDS */
+		.label    = SECO_VIDEO_LABEL_LVDSx2,
+		.video = {
+			{ VIDEO_USED, VIDEO_LVDSx2, NO_VIDEO_ARGS },
+		},
+		.panel_name = "none",
+		.dtbo_conf_file = STR(ENV_DTBO_C25_LVDS_DUAL),
+		.use_bootargs = 0,
+	}, {
+		/* DP */
+		.label    = SECO_VIDEO_LABEL_DP,
+		.video = {
+			{ VIDEO_USED, VIDEO_HDMI, NO_VIDEO_ARGS },
+		},
+		.panel_name = "none",
+		.dtbo_conf_file = STR(ENV_DTBO_C25_DP),
+		.use_bootargs = 0,
+	}, {
+		/* eDP */
+		.label    = SECO_VIDEO_LABEL_EDP,
+		.video = {
+			{ VIDEO_USED, VIDEO_EDP, NO_VIDEO_ARGS },
+		},
+		.panel_name = "none",
+		.dtbo_conf_file = STR(ENV_DTBO_C25_EDP),
+		.use_bootargs = 0,
+	},
+};
+
+size_t video_mode_size_CFG_1 = ARRAY_SIZE(video_mode_list_CFG_1);
+
+
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+/* *********************************** FDT OVERLAY *********************************** */
+
+/* PCIE, CANRTC, Q7SPI, UART4 */
+overlay_list_t overlay_peripheral_list_CFG_0[] = {
+	{
+		.title = "pcie support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "pcie", STR(ENV_DTBO_C25_PCIE) },
+		},
+	}, {
+		.title = "can/rtc support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "can/rtc", STR(ENV_DTBO_C25_CAN_RTC) },
+		},
+	}, {
+		.title = "q7 spi support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "q7 spi", STR(ENV_DTBO_C25_Q7_SPI) },
+		},
+	}, {
+		.title = "uart4 support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "uart4", STR(ENV_DTBO_C25_UART4) },
+		},
+	},
+};
+
+size_t overlay_peripheral_size_CFG_0 = ARRAY_SIZE(overlay_peripheral_list_CFG_0);
+
+
+/* PCIE, CANRTC, Q7SPI */
+overlay_list_t overlay_peripheral_list_CFG_1[] = {
+	{
+		.title = "pcie support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "pcie", STR(ENV_DTBO_C25_PCIE) },
+		},
+	}, {
+		.title = "can/rtc support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "can/rtc", STR(ENV_DTBO_C25_CAN_RTC) },
+		},
+	}, {
+		.title = "q7 spi support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "q7 spi", STR(ENV_DTBO_C25_Q7_SPI) },
+		},
+	},
+};
+
+size_t overlay_peripheral_size_CFG_1 = ARRAY_SIZE(overlay_peripheral_list_CFG_1);
+
+
+/* PCIE, CANRTC, UART4 */
+overlay_list_t overlay_peripheral_list_CFG_2[] = {
+	{
+		.title = "pcie support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "pcie", STR(ENV_DTBO_C25_PCIE) },
+		},
+	}, {
+		.title = "can/rtc support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "can/rtc", STR(ENV_DTBO_C25_CAN_RTC) },
+		},
+	}, {
+		.title = "uart4 support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "uart4", STR(ENV_DTBO_C25_UART4) },
+		},
+	},
+};
+
+size_t overlay_peripheral_size_CFG_2 = ARRAY_SIZE(overlay_peripheral_list_CFG_2);
+
+
+/* PCIE, Q7SPI, UART4 */
+overlay_list_t overlay_peripheral_list_CFG_3[] = {
+	{
+		.title = "pcie support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "pcie", STR(ENV_DTBO_C25_PCIE) },
+		},
+	}, {
+		.title = "q7 spi support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "q7 spi", STR(ENV_DTBO_C25_Q7_SPI) },
+		},
+	}, {
+		.title = "uart4 support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "uart4", STR(ENV_DTBO_C25_UART4) },
+		},
+	},
+};
+
+size_t overlay_peripheral_size_CFG_3 = ARRAY_SIZE(overlay_peripheral_list_CFG_3);
+
+
+/* PCIE, CANRTC  */
+overlay_list_t overlay_peripheral_list_CFG_4[] = {
+	{
+		.title = "pcie support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "pcie", STR(ENV_DTBO_C25_PCIE) },
+		},
+	}, {
+		.title = "can/rtc support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "can/rtc", STR(ENV_DTBO_C25_CAN_RTC) },
+		},
+	},
+};
+
+size_t overlay_peripheral_size_CFG_4 = ARRAY_SIZE(overlay_peripheral_list_CFG_4);
+
+
+/* PCIE, Q7SPI */
+overlay_list_t overlay_peripheral_list_CFG_5[] = {
+	{
+		.title = "pcie support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "pcie", STR(ENV_DTBO_C25_PCIE) },
+		},
+	}, {
+		.title = "q7 spi support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "q7 spi", STR(ENV_DTBO_C25_Q7_SPI) },
+		},
+	},
+};
+
+size_t overlay_peripheral_size_CFG_5 = ARRAY_SIZE(overlay_peripheral_list_CFG_5);
+
+
+/* PCIE, UART4 */
+overlay_list_t overlay_peripheral_list_CFG_6[] = {
+	{
+		.title = "pcie support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "pcie", STR(ENV_DTBO_C25_PCIE) },
+		},
+	}, {
+		.title = "uart4 support",
+		.options = {
+			{ "not use", "" }, // default
+			{ "uart4", STR(ENV_DTBO_C25_UART4) },
+		},
+	},
+};
+
+size_t overlay_peripheral_size_CFG_6 = ARRAY_SIZE(overlay_peripheral_list_CFG_6);
+
+
+#endif  /* CONFIG_OF_LIBFDT_OVERLAY */

board/seco/imx8mq_c25/imx8mq_c25.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 SECO
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <dwc3-uboot.h>
+#include <linux/delay.h>
+
+#include "../common/proto_seco.h"
+#include "seco/seco_env_gd.h"
+
+#include "strap_cfg.h"
+
+#ifdef CONFIG_SECO_ENV_MANAGER
+#include <seco/env_common.h>
+#include "env_conf.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define NAND_PAD_CTRL		(PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS)
+#define NAND_PAD_READY0_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE)
+
+#define UART_PAD_CTRL		(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL		(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+#define PULLUP_PAD_CTRL		(PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+static iomux_v3_cfg_t const misc_pads[] = {
+	IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 | MUX_PAD_CTRL(PULLUP_PAD_CTRL), /* RTC_INT_CPU  */
+};
+
+static iomux_v3_cfg_t const video_disable_pads[] = {
+	IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 | MUX_PAD_CTRL(PULLUP_PAD_CTRL),
+};
+
+void video_bridge_disable(void)
+{
+	imx_iomux_v3_setup_multiple_pads(video_disable_pads, ARRAY_SIZE(video_disable_pads));
+
+	gpio_request(IMX_GPIO_NR(3, 19), "PD-BRIDGE");
+	gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
+}
+
+#ifdef CONFIG_USB_DWC3
+
+static iomux_v3_cfg_t const usb_c25_pads[] = {
+	IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+int board_qspi_init(void)
+{
+	set_clk_qspi();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+#ifdef CONFIG_SPL_BUILD
+static iomux_v3_cfg_t const gpmi_pads[] = {
+	IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+	IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+};
+#endif
+
+static void setup_gpmi_nand(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+#endif
+
+	init_nand_clk();
+}
+#endif
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+/*  __________________________________________________________________________
+ * |                                                                          |
+ * |                               BOOT DEVICE                                |
+ * |__________________________________________________________________________|
+ */
+boot_mem_dev_t boot_mem_dev_list[SECO_NUM_BOOT_DEV] = {
+	{ MMC1_BOOT, SECO_DEV_LABEL_EMMC },
+};
+
+int usdhc_devno[2] = { BOARD_BOOT_ID_EMMC, -1};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand(); /* SPL will call the board_early_init_f */
+#endif
+	/* Misc Pads Init */
+	imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_DWC3
+void usb_seco_c25_init(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_c25_pads, ARRAY_SIZE(usb_c25_pads));
+
+	gpio_request(IMX_GPIO_NR(4, 22), "usb-hub-reset-c25");
+	gpio_request(IMX_GPIO_NR(4, 19), "sd2_p_en-c25");
+
+	/* USB hub reset*/
+	gpio_direction_output(IMX_GPIO_NR(4, 22), 1);
+	gpio_direction_output(IMX_GPIO_NR(4, 19), 0);
+}
+#endif
+
+int dram_init(void)
+{
+	unsigned long long sdram_size;
+
+	if (C25_IS_1GB)
+		sdram_size = PHYS_DRAM_IS_1GB;
+	if (C25_IS_2GB)
+		sdram_size = PHYS_DRAM_IS_2GB;
+	if (C25_IS_4GB)
+		sdram_size = PHYS_DRAM_IS_3GB;
+	/* rom_pointer[1] contains the size of TEE occupies */
+	if (rom_pointer[1])
+		gd->ram_size = sdram_size - rom_pointer[1];
+	else
+		gd->ram_size = sdram_size;
+
+#if CONFIG_NR_DRAM_BANKS > 1
+	if (C25_IS_4GB)
+		gd->ram_size += PHYS_SDRAM_2_SIZE;
+#endif
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	unsigned long long sdram_size;
+
+	if (C25_IS_1GB)
+		sdram_size = PHYS_DRAM_IS_1GB;
+	if (C25_IS_2GB)
+		sdram_size = PHYS_DRAM_IS_2GB;
+	if (C25_IS_4GB)
+		sdram_size = PHYS_DRAM_IS_3GB ; /* Actually the Kernel supports MAX 3GB of RAM */
+	if (C25_IS_8GB)
+		sdram_size = PHYS_DRAM_IS_3GB ; /* Actually the Kernel supports MAX 3GB of RAM */
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	if (rom_pointer[1])
+		gd->bd->bi_dram[0].size = sdram_size - rom_pointer[1];
+	else
+		gd->bd->bi_dram[0].size = sdram_size;
+
+#if CONFIG_NR_DRAM_BANKS > 1
+	if (C25_IS_4GB) {
+		gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+		gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	}
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	c25_fdt_ram_setup(blob, bd);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+#define FEC_RST_PAD		IMX_GPIO_NR(4, 3)
+
+static iomux_v3_cfg_t const fec1_rst_pads[] = {
+	IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, ARRAY_SIZE(fec1_rst_pads));
+
+	gpio_request(FEC_RST_PAD, "fec1_rst");
+	gpio_direction_output(FEC_RST_PAD, 0);
+	udelay(10);
+	gpio_direction_output(FEC_RST_PAD, 1);
+}
+
+static int setup_fec(void)
+{
+	setup_iomux_fec();
+
+	return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_DWC3
+
+#define USB_PHY_CTRL0			0xF0040
+#define USB_PHY_CTRL0_REF_SSP_EN	BIT(2)
+
+#define USB_PHY_CTRL1			0xF0044
+#define USB_PHY_CTRL1_RESET		BIT(0)
+#define USB_PHY_CTRL1_COMMONONN		BIT(1)
+#define USB_PHY_CTRL1_ATERESET		BIT(3)
+#define USB_PHY_CTRL1_VDATSRCENB0	BIT(19)
+#define USB_PHY_CTRL1_VDATDETENB0	BIT(20)
+
+#define USB_PHY_CTRL2			0xF0048
+#define USB_PHY_CTRL2_TXENABLEN0	BIT(8)
+
+static struct dwc3_device dwc3_device_data = {
+#ifdef CONFIG_SPL_BUILD
+	.maximum_speed = USB_SPEED_HIGH,
+#else
+	.maximum_speed = USB_SPEED_SUPER,
+#endif
+	.base = USB1_BASE_ADDR,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+	.power_down_scale = 2,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+	dwc3_uboot_handle_interrupt(index);
+	return 0;
+}
+
+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
+{
+	u32 RegData;
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+			USB_PHY_CTRL1_COMMONONN);
+	RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL0);
+	RegData |= USB_PHY_CTRL0_REF_SSP_EN;
+	writel(RegData, dwc3->base + USB_PHY_CTRL0);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL2);
+	RegData |= USB_PHY_CTRL2_TXENABLEN0;
+	writel(RegData, dwc3->base + USB_PHY_CTRL2);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		imx8m_usb_power(index, true);
+		dwc3_nxp_usb_phy_init(&dwc3_device_data);
+		return dwc3_uboot_init(&dwc3_device_data);
+	}
+
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		dwc3_uboot_exit(index);
+		imx8m_usb_power(index, false);
+	}
+
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	print_bootinfo();
+
+	strap_show();
+
+	return 0;
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+	init_usb_clk();
+	usb_seco_c25_init();
+#endif
+
+	video_bridge_disable();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "SECO_C25");
+	env_set("board_rev", "iMX8MQ");
+#endif
+
+	/* seco_config variables */
+#ifdef CONFIG_SECO_ENV_MANAGER
+	gd->bsp_sources.kern_dev_list		= &kern_dev_imx8_list[0];
+	gd->bsp_sources.kern_dev_num		= kern_dev_imx8_size;
+	gd->bsp_sources.fdt_dev_list		= &fdt_dev_imx8_list[0];
+	gd->bsp_sources.fdt_dev_num		= fdt_dev_imx8_size;
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+	gd->bsp_sources.fdt_overlay_dev_list	= fdt_overlay_dev_imx8_list;
+	gd->bsp_sources.fdt_overlay_dev_num	= fdt_overlay_dev_imx8_size;
+#endif
+	gd->bsp_sources.ramfs_dev_list		= &ramfs_dev_imx8_list[0];
+	gd->bsp_sources.ramfs_dev_num		= ramfs_dev_imx8_size;
+	gd->bsp_sources.filesystem_dev_list	= &filesystem_dev_imx8_list[0];
+	gd->bsp_sources.filesystem_dev_num	= filesystem_dev_imx8_size;
+
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+	if (C25_HAS_HDMI) {
+		gd->boot_setup.video_mode_list		= video_mode_list_CFG_0;
+		gd->boot_setup.video_mode_num		= video_mode_size_CFG_0;
+	} else {
+		gd->boot_setup.video_mode_list		= video_mode_list_CFG_1;
+		gd->boot_setup.video_mode_num		= video_mode_size_CFG_1;
+	}
+	if (C25_HAS_CANRTC && C25_HAS_Q7SPI && C25_HAS_UART4) {
+		gd->boot_setup.overlay_peripheral_list	= overlay_peripheral_list_CFG_0;
+		gd->boot_setup.overlay_peripheral_num	= overlay_peripheral_size_CFG_0;
+	} else if (C25_HAS_CANRTC && C25_HAS_Q7SPI) {
+		gd->boot_setup.overlay_peripheral_list	= overlay_peripheral_list_CFG_1;
+		gd->boot_setup.overlay_peripheral_num	= overlay_peripheral_size_CFG_1;
+	} else if (C25_HAS_CANRTC && C25_HAS_UART4) {
+		gd->boot_setup.overlay_peripheral_list	= overlay_peripheral_list_CFG_2;
+		gd->boot_setup.overlay_peripheral_num	= overlay_peripheral_size_CFG_2;
+	} else if (C25_HAS_Q7SPI && C25_HAS_UART4) {
+		gd->boot_setup.overlay_peripheral_list	= overlay_peripheral_list_CFG_3;
+		gd->boot_setup.overlay_peripheral_num	= overlay_peripheral_size_CFG_3;
+	} else if (C25_HAS_CANRTC) {
+		gd->boot_setup.overlay_peripheral_list	= overlay_peripheral_list_CFG_4;
+		gd->boot_setup.overlay_peripheral_num	= overlay_peripheral_size_CFG_4;
+	} else if (C25_HAS_Q7SPI) {
+		gd->boot_setup.overlay_peripheral_list	= overlay_peripheral_list_CFG_5;
+		gd->boot_setup.overlay_peripheral_num	= overlay_peripheral_size_CFG_5;
+	} else {
+		gd->boot_setup.overlay_peripheral_list	= overlay_peripheral_list_CFG_6;
+		gd->boot_setup.overlay_peripheral_num	= overlay_peripheral_size_CFG_6;
+	}
+#endif
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	return 0;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+	unsigned long long sdram_size;
+
+	if (C25_IS_1GB)
+		sdram_size = PHYS_DRAM_IS_1GB;
+	if (C25_IS_2GB)
+		sdram_size = PHYS_DRAM_IS_2GB;
+	if (C25_IS_4GB)
+		sdram_size = PHYS_DRAM_IS_3GB;
+	if (rom_pointer[1])
+		return (sdram_size - rom_pointer[1]);
+	else
+		return sdram_size;
+}

board/seco/imx8mq_c25/spl.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 SECO
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <spl.h>
+#include "../common/pfuze.h"
+#include <nand.h>
+
+#include "ddr/ddr.h"
+
+#include "strap_cfg.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_dram_init(void)
+{
+	/* ddr init */
+	if (C25_IS_1GB)
+		printf("C25 is 1GB\n");
+	else if (C25_IS_2GB)
+		printf("C20 is 2GB\n");
+	else if (C25_IS_4GB)
+		printf("C25 is 4GB\n");
+
+	ddr_init(NULL);
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#define USDHC2_CD_GPIO			IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO			IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO			IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = 1;
+		break;
+
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC	0
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return -ENODEV;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return -ENODEV;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+	pmic_reg_read(p, PFUZE100_SW1ABVOL, &reg);
+	if ((reg & 0x3f) != 0x1c) {
+		reg &= ~0x3f;
+		reg |= 0x1c;
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, reg);
+	}
+
+	pmic_reg_read(p, PFUZE100_SW1CVOL, &reg);
+	if ((reg & 0x3f) != 0x1c) {
+		reg &= ~0x3f;
+		reg |= 0x1c;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, reg);
+	}
+
+	ret = pfuze_mode_init(p, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+#ifndef CONFIG_SPL_USB_SDP_SUPPORT
+	/* Serial download mode */
+	if (is_usb_boot()) {
+		puts("Back to ROM, SDP\n");
+		restore_boot_params();
+	}
+#endif
+
+	init_usb_clk();
+
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	arch_cpu_init();
+
+	init_uart_clk(0); /* Init UART0 clock */
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* Adjust pmic voltage VDD_DRAM to 1.0V for DRAM RUN >= 2400MHZ */
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}

board/seco/imx8mq_c25/strap_cfg.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 SECO
+ *
+ * Reading C25 Board type
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include "strap_cfg.h"
+
+#define PULLUP_PAD_CTRL  (PAD_CTL_PUE)
+
+/* ____________________________________________________________________________
+ *|                                                                            |
+ *|                                  C25 REVISION                              |
+ *|____________________________________________________________________________|
+ */
+
+#define C25_IOMUX_REG(x)	((x))
+#define C25_PADCTRL_REG(x)	((x))
+#define C25_GDIR_REG_IN(x, n)	writel((readl(x + 0x4)) & ~(1<<n), x + 0x4)
+#define C25_PSR_REG(x, n)	(readl(x + 0x8) & (1<<n))
+
+#define shift_0			0
+#define shift_1			1
+#define shift_2			2
+#define shift_3			3
+#define shift_4			4
+#define shift_5			5
+#define shift_6			6
+#define shift_7			7
+#define shift_8			8
+#define shift_9			9
+#define shift_10		10
+
+#define GPIO3_PAD_BASE		0x30220000
+#define GPIO_CFG_0		16
+#define GPIO_CFG_1		18
+#define GPIO_CFG_2		17
+#define GPIO_CFG_3		15
+#define GPIO_CFG_4		14
+#define GPIO_CFG_5		4
+#define GPIO_CFG_6		3
+#define GPIO_CFG_7		2
+#define GPIO_CFG_8		10
+#define GPIO_CFG_9		11
+#define GPIO_CFG_10		12
+
+struct sizes {
+	u32 s0;
+	u32 s1;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+iomux_v3_cfg_t const board_conf_pads[] = {
+	/* RAM CONFIG */
+	IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16	| MUX_PAD_CTRL(PULLUP_PAD_CTRL),	/* cfg_0 */
+	IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18	| MUX_PAD_CTRL(PULLUP_PAD_CTRL),	/* cfg_1 */
+	/* Undefined */
+	IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17	| MUX_PAD_CTRL(PULLUP_PAD_CTRL),	/* cfg_2 */
+	IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15	| MUX_PAD_CTRL(PULLUP_PAD_CTRL),	/* cfg_3 */
+	IMX8MQ_PAD_NAND_DQS__GPIO3_IO14		| MUX_PAD_CTRL(PULLUP_PAD_CTRL),	/* cfg_4 */
+	IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4	| MUX_PAD_CTRL(PULLUP_PAD_CTRL),	/* cfg_5 */
+	IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3	| MUX_PAD_CTRL(PULLUP_PAD_CTRL),	/* cfg_6 */
+	IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2	| MUX_PAD_CTRL(PULLUP_PAD_CTRL),	/* cfg_7 */
+	IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10	| MUX_PAD_CTRL(PULLUP_PAD_CTRL),	/* cfg_8 */
+	IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11	| MUX_PAD_CTRL(PULLUP_PAD_CTRL),	/* cfg_9 */
+	IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12	| MUX_PAD_CTRL(PULLUP_PAD_CTRL),	/* cfg_10 */
+};
+
+int c25_get_board_configuration(void)
+{
+	ulong value = 0;
+
+	/*
+	 *
+	 * CFG code is composed in this way:
+	 * cfg_0 -> first bit	X
+	 * cfg_1 -> second bit	X
+	 * cfg_2 -> third bit	X
+	 *
+	 */
+
+	imx_iomux_v3_setup_multiple_pads(board_conf_pads, ARRAY_SIZE(board_conf_pads));
+
+	/* Mux as Input */
+	C25_GDIR_REG_IN(GPIO3_PAD_BASE, GPIO_CFG_0);
+	C25_GDIR_REG_IN(GPIO3_PAD_BASE, GPIO_CFG_1);
+	C25_GDIR_REG_IN(GPIO3_PAD_BASE, GPIO_CFG_2);
+	C25_GDIR_REG_IN(GPIO3_PAD_BASE, GPIO_CFG_3);
+	C25_GDIR_REG_IN(GPIO3_PAD_BASE, GPIO_CFG_4);
+	C25_GDIR_REG_IN(GPIO3_PAD_BASE, GPIO_CFG_5);
+	C25_GDIR_REG_IN(GPIO3_PAD_BASE, GPIO_CFG_6);
+	C25_GDIR_REG_IN(GPIO3_PAD_BASE, GPIO_CFG_7);
+	C25_GDIR_REG_IN(GPIO3_PAD_BASE, GPIO_CFG_8);
+	C25_GDIR_REG_IN(GPIO3_PAD_BASE, GPIO_CFG_9);
+	C25_GDIR_REG_IN(GPIO3_PAD_BASE, GPIO_CFG_10);
+
+	/* Read Conf value */
+	value = (C25_PSR_REG(GPIO3_PAD_BASE, GPIO_CFG_0) >> GPIO_CFG_0) << shift_0 |
+		(C25_PSR_REG(GPIO3_PAD_BASE, GPIO_CFG_1) >> GPIO_CFG_1) << shift_1 |
+		(C25_PSR_REG(GPIO3_PAD_BASE, GPIO_CFG_2) >> GPIO_CFG_2) << shift_2 |
+		(C25_PSR_REG(GPIO3_PAD_BASE, GPIO_CFG_3) >> GPIO_CFG_3) << shift_3 |
+		(C25_PSR_REG(GPIO3_PAD_BASE, GPIO_CFG_4) >> GPIO_CFG_4) << shift_4 |
+		(C25_PSR_REG(GPIO3_PAD_BASE, GPIO_CFG_5) >> GPIO_CFG_5) << shift_5 |
+		(C25_PSR_REG(GPIO3_PAD_BASE, GPIO_CFG_6) >> GPIO_CFG_6) << shift_6 |
+		(C25_PSR_REG(GPIO3_PAD_BASE, GPIO_CFG_7) >> GPIO_CFG_7) << shift_7 |
+		(C25_PSR_REG(GPIO3_PAD_BASE, GPIO_CFG_8) >> GPIO_CFG_8) << shift_8 |
+		(C25_PSR_REG(GPIO3_PAD_BASE, GPIO_CFG_9) >> GPIO_CFG_9) << shift_9 |
+		(C25_PSR_REG(GPIO3_PAD_BASE, GPIO_CFG_10) >> GPIO_CFG_10) << shift_10;
+
+	return value;
+}
+
+int strap_get_ram_cfg(void)
+{
+	return c25_get_board_configuration() & 0b11;
+}
+
+int strap_get_video_cfg(void)
+{
+	return !((c25_get_board_configuration() >> 2) & 0b1);
+};
+
+int strap_get_wifi_cfg(void)
+{
+	return !((c25_get_board_configuration() >> 4) & 0b1);
+};
+
+int strap_get_canrtc_cfg(void)
+{
+	/* true for conf = 0x0, conf = 0x2, conf = 0x3 */
+	return !((!((c25_get_board_configuration() >> 6) & 0b1)) & ((c25_get_board_configuration() >> 5) & 0b1));
+};
+
+int strap_get_uart4_cfg(void)
+{
+	/* true for conf = 0x0 */
+	return (!((c25_get_board_configuration() >> 6) & 0b1)) & !((c25_get_board_configuration() >> 5) & 0b1);
+};
+
+int strap_get_q7spi_cfg(void)
+{
+	return ((c25_get_board_configuration() >> 5) & 0b1);
+};
+
+int strap_get_cpu_cfg(void)
+{
+	return C25_IS_1GB;
+};
+
+void strap_show(void)
+{
+	strap_conf_t c25_strap_conf;
+
+	c25_strap_conf.ram_size = GET_C25_RAM_STRAPS;
+	c25_strap_conf.video = GET_C25_HDMI_STRAPS;
+	c25_strap_conf.wifi = GET_C25_WIFI_STRAPS;
+	c25_strap_conf.canrtc = GET_C25_CANRTC_STRAPS;
+	c25_strap_conf.uart4 = GET_C25_UART4_STRAPS;
+	c25_strap_conf.q7spi = GET_C25_Q7SPI_STRAPS;
+	c25_strap_conf.cpu = GET_C25_CPU_STRAPS;
+
+	printf("Straps: 0x%x\n", c25_get_board_configuration());
+
+	printf(" - RAM code: %d (", c25_strap_conf.ram_size);
+	switch (c25_strap_conf.ram_size) {
+	case RAM_1GB:
+		printf("1GB");
+		break;
+	case RAM_2GB:
+		printf("2GB");
+		break;
+	case RAM_4GB:
+		printf("4GB");
+		break;
+	case RAM_8GB:
+		printf("8GB");
+		break;
+	default:
+		printf("Unknown");
+		break;
+	}
+	printf(")\n");
+
+	printf(" - HDMI code: %d (", c25_strap_conf.video);
+	switch (c25_strap_conf.video) {
+	case YES_HDMI:
+		printf("HDMI");
+		break;
+	case NO_HDMI:
+		printf("NO HDMI");
+		break;
+	default:
+		printf("Unknown");
+		break;
+	}
+	printf(")\n");
+
+	printf(" - WIFI code: %d (", c25_strap_conf.wifi);
+	switch (c25_strap_conf.wifi) {
+	case YES_WIFI:
+		printf("WIFI");
+		break;
+	case NO_WIFI:
+		printf("NO WIFI");
+		break;
+	default:
+		printf("Unknown");
+		break;
+	}
+	printf(")\n");
+
+	printf(" - CANRTC code: %d (", c25_strap_conf.canrtc);
+	switch (c25_strap_conf.wifi) {
+	case YES_CANRTC:
+		printf("CANRTC");
+		break;
+	case NO_CANRTC:
+		printf("NO CANRTC");
+		break;
+	default:
+		printf("Unknown");
+		break;
+	}
+	printf(")\n");
+
+	printf(" - UART4 code: %d (", c25_strap_conf.uart4);
+	switch (c25_strap_conf.uart4) {
+	case YES_UART4:
+		printf("UART4");
+		break;
+	case NO_UART4:
+		printf("NO UART4");
+		break;
+	default:
+		printf("Unknown");
+		break;
+	}
+	printf(")\n");
+
+	printf(" - Q7SPI code: %d (", c25_strap_conf.q7spi);
+	switch (c25_strap_conf.q7spi) {
+	case YES_Q7SPI:
+		printf("Q7SPI");
+		break;
+	case NO_Q7SPI:
+		printf("NO Q7SPI");
+		break;
+	default:
+		printf("Unknown");
+		break;
+	}
+	printf(")\n");
+
+	printf(" - CPU code: %d (", c25_strap_conf.cpu);
+	switch (c25_strap_conf.cpu) {
+	case YES_CPUQL:
+		printf("QUADLITE");
+		break;
+	case YES_CPUQ:
+		printf("QUAD/DUAL");
+		break;
+	default:
+		printf("Unknown");
+		break;
+	}
+	printf(")\n");
+}
+
+/* Substitute in the fdt kernel file the right dram setup */
+void c25_fdt_ram_setup(void *blob, struct bd_info *bdev)
+{
+	int offset, ret;
+	struct sizes ssize;
+
+	printf("Overlay dts /reserved-memory/linux,cma/: size = ");
+	offset = fdt_path_offset(blob, "/reserved-memory/linux,cma/");
+	if (offset < 0) {
+		printf("ERROR: find node /: %s.\n", fdt_strerror(offset));
+		return;
+	}
+	if (C25_IS_1GB) {
+		ssize.s0 = cpu_to_fdt32(0x0);
+		ssize.s1 = cpu_to_fdt32(0x14000000);
+		printf("<0x0 0x14000000>\n");
+	}
+	if (C25_IS_2GB) {
+		ssize.s0 = cpu_to_fdt32(0x0);
+		ssize.s1 = cpu_to_fdt32(0x20000000);
+		printf("<0x0 0x20000000>\n");
+	}
+	if (C25_IS_4GB) {
+		ssize.s0 = cpu_to_fdt32(0x0);
+		ssize.s1 = cpu_to_fdt32(0x3c000000);
+		printf("<0x0 0x3c000000>\n");
+	}
+
+	ret = fdt_setprop(blob, offset, "size", &ssize, sizeof(ssize));
+	if (ret < 0)
+		printf("ERROR: could not update revision property %s.\n",
+			fdt_strerror(ret));
+}

board/seco/imx8mq_c25/strap_cfg.h

+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 SECO
+ */
+
+#ifndef _C25_REVISION_H_
+#define _C25_REVISION_H_
+
+int strap_get_ram_cfg(void);
+int strap_get_video_cfg(void);
+int strap_get_wifi_cfg(void);
+int strap_get_canrtc_cfg(void);
+int strap_get_q7spi_cfg(void);
+int strap_get_uart4_cfg(void);
+int strap_get_cpu_cfg(void);
+
+void c25_fdt_ram_setup(void *blob, struct bd_info *bdev);
+
+void strap_show(void);
+
+typedef enum {
+	RAM_1GB = 0x0,
+	RAM_2GB = 0x1,
+	RAM_4GB = 0x2,
+	RAM_8GB = 0x3,
+} RAM_STRAPS;
+
+typedef enum {
+	NO_HDMI = 0x0,
+	YES_HDMI = 0x1,
+} HDMI_STRAPS;
+
+typedef enum {
+	NO_WIFI = 0x0,
+	YES_WIFI = 0x1,
+} WIFI_STRAPS;
+
+typedef enum {
+	NO_CANRTC = 0x0,
+	YES_CANRTC = 0x1,
+} CANRTC_STRAPS;
+
+typedef enum {
+	NO_UART4 = 0x0,
+	YES_UART4 = 0x1,
+} UART4_STRAPS;
+
+typedef enum {
+	NO_Q7SPI = 0x0,
+	YES_Q7SPI = 0x1,
+} Q7SPI_STRAPS;
+
+typedef enum {
+	YES_CPUQ = 0x0,
+	YES_CPUQL = 0x1,
+} CPU_STRAPS;
+
+typedef struct {
+	u8 ram_size;
+	u8 video;
+	u8 wifi;
+	u8 canrtc;
+	u8 uart4;
+	u8 q7spi;
+	u8 cpu;
+} strap_conf_t;
+
+#define GET_C25_RAM_STRAPS	(strap_get_ram_cfg())
+#define C25_IS_1GB		(GET_C25_RAM_STRAPS == RAM_1GB)
+#define C25_IS_2GB		(GET_C25_RAM_STRAPS == RAM_2GB)
+#define C25_IS_4GB		(GET_C25_RAM_STRAPS == RAM_4GB)
+#define C25_IS_8GB		(GET_C25_RAM_STRAPS == RAM_8GB)
+
+#define GET_C25_HDMI_STRAPS	(strap_get_video_cfg())
+#define C25_HAS_HDMI		(GET_C25_HDMI_STRAPS == YES_HDMI)
+
+#define GET_C25_WIFI_STRAPS	(strap_get_wifi_cfg())
+#define C25_HAS_WIFI		(GET_C25_WIFI_STRAPS == YES_WIFI)
+
+#define GET_C25_CANRTC_STRAPS	(strap_get_canrtc_cfg())
+#define C25_HAS_CANRTC		(GET_C25_CANRTC_STRAPS == YES_CANRTC)
+
+#define GET_C25_UART4_STRAPS	(strap_get_uart4_cfg())
+#define C25_HAS_UART4		(GET_C25_UART4_STRAPS == YES_UART4)
+
+#define GET_C25_Q7SPI_STRAPS	(strap_get_q7spi_cfg())
+#define C25_HAS_Q7SPI		(GET_C25_Q7SPI_STRAPS == YES_Q7SPI)
+
+#define GET_C25_CPU_STRAPS	(strap_get_cpu_cfg())
+#define C25_HAS_CPUQL		(GET_C25_CPU_STRAPS == YES_CPUQL)
+#define C25_HAS_CPUQ		(GET_C25_CPU_STRAPS == YES_CPUQ)
+
+#endif

configs/seco_imx8mq_c25_defconfig

+# PROCESSOR
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_MXC_GPIO=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_IMX_TMU=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+
+# SYSTEM
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_SECO_IMX8MQ_C25=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_HUSH_PARSER=y
+
+# ENVIRONMENT
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SECO_ENV_MANAGER=y
+CONFIG_SECO_ECOSYSTEM=y
+CONFIG_SECO_ECOSYSTEM_TARGET="c25"
+
+# SPL
+CONFIG_SPL=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_CSF_SIZE=0x2000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x300
+
+# FDT
+CONFIG_DEFAULT_DEVICE_TREE="seco-imx8mq-c25"
+CONFIG_DEFAULT_FDT_FILE="seco-imx8mq-c25.dtb"
+CONFIG_OF_LIST="seco-imx8mq-c25"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_DM_ETH=y
+CONFIG_DM_THERMAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_OF_BOARD_SETUP=y
+
+# MMC
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+
+# USB
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_DM_USB=y
+CONFIG_USB=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+
+# I2C
+
+# MTD
+CONFIG_MTD=y
+
+# SPI
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SPI=y
+CONFIG_FSL_QSPI=y
+
+# ETHERNET
+CONFIG_PHY=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+
+# STORAGE
+CONFIG_EFI_PARTITION=y
+CONFIG_CMD_FS_GENERIC=y
+
+# PCI
+
+# VIDEO
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_SPLASH_SOURCE=y
+
+# COMMANDS
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_REGULATOR=y
+
+# FASTBOOT
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=0

include/configs/seco_imx8mq_c25.h

+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 SECO
+ */
+
+#ifndef __SECO_MX8MQ_C25_CONFIG_H
+#define __SECO_MX8MQ_C25_CONFIG_H
+
+#include "seco_mx8mq_common.h"
+#include <linux/stringify.h>
+
+
+/* ____________________________________________________________________________
+ *|                                                                            |
+ *|                                   WATCHDOG                                 |
+ *|____________________________________________________________________________|
+ */
+
+#define CONFIG_REMAKE_ELF
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_FEC_MXC)
+#define CONFIG_ETHPRIME					"FEC"
+#define PHY_ANEG_TIMEOUT				20000
+#define FEC_QUIRK_ENET_MAC
+#define IMX_FEC_BASE					0x30BE0000
+#define CONFIG_FEC_XCV_TYPE				RGMII
+#define CONFIG_FEC_MXC_PHYADDR				9
+#endif
+
+
+#define CONFIG_SYS_MMC_ENV_DEV				0   /* USDHC1 - eMMC */
+#define CONFIG_MMCROOT					"/dev/mmcblk0p2"  /* USDHC1 - eMMC */
+
+#define CONFIG_BAUDRATE					115200
+
+#define CONFIG_MXC_UART_BASE				UART1_BASE_ADDR
+
+
+#define CONFIG_SYS_FSL_USDHC_NUM			2
+#define CONFIG_SYS_FSL_ESDHC_ADDR			0
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART			1
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C_SPEED				100000
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE			1
+#define CONFIG_SYS_NAND_BASE				0x20000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#endif /* CONFIG_NAND_MXS */
+
+/* USB configs */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USB_MAX_CONTROLLER_COUNT			1
+#define CONFIG_CMD_USB
+#define CONFIG_USBD_HS
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_GADGET_VBUS_DRAW			2
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#endif
+
+#define CONFIG_SERIAL_TAG
+
+
+/* ____________________________________________________________________________
+ *|                                                                            |
+ *|                                 ENVIRONMENT                                |
+ *|____________________________________________________________________________|
+ */
+
+#define ENV_MMCAUTODETECT				"yes"
+#define ENV_FDTAUTODETECT				"yes"
+#define ENV_MEMAUTODETECT				"yes"
+
+
+#define SCFG_DEFAULT_FDT_IMX8_FILE			"seco-imx8mq-c25.dtb"
+#define ENV_DEFAULT_FDT_FILE				"seco-imx8mq-c25.dtb"
+
+#define ENV_CONSOLE_DEV					"ttymxc0"
+
+#define SECO_NUM_BOOT_DEV				1  // eMMC
+
+/*  SCFG = SECO CONFIG  */
+#define BOARD_BOOT_ID_EMMC				0
+#define BOARD_BOOT_ID_SD				1
+#define BOARD_BOOT_ID_SD_EXT				2
+
+
+#define BOARD_ROOT_ID_EMMC				0
+#define BOARD_ROOT_ID_SD				1
+#define BOARD_ROOT_ID_SD_EXT				2
+
+
+#define SCFG_BOOT_DEV_ID_EMMC				__stringify(BOARD_BOOT_ID_EMMC)"\0"
+#define SCFG_BOOT_DEV_ID_SD				__stringify(BOARD_BOOT_ID_SD)"\0"
+#define SCFG_BOOT_DEV_ID_SD_EXT				__stringify(BOARD_BOOT_ID_SD_EXT)"\0"
+#define SCFG_BOOT_DEV_ID_SPI				"0"
+#define SCFG_BOOT_DEV_ID_SATA				"0"
+#define SCFG_BOOT_DEV_ID_USB				"0"
+
+#define SCFG_ROOT_DEV_ID_EMMC				__stringify(BOARD_ROOT_ID_EMMC)"\0"
+#define SCFG_ROOT_DEV_ID_SD				__stringify(BOARD_ROOT_ID_SD)"\0"
+#define SCFG_ROOT_DEV_ID_SD_EXT				__stringify(BOARD_BOOT_ID_SD_EXT)"\0"
+#define SCFG_ROOT_DEV_ID_SATA				"0"
+#define SCFG_ROOT_DEV_ID_USB				"0"
+
+
+#define SCFG_SET_VIDEOMODE				1 /* if 0 not video setting in seco_config */
+
+/* Defaults devices and partitions sources */
+
+/*  boot file partition location  */
+#define ENV_SYS_MMC_ENV_DEV				0
+#define ENV_SYS_MMC_KERNEL_PART				1
+#define ENV_SYS_MMC_FDT_PART				1
+#define ENV_SYS_MMC_RAMFS_PART				1
+/*  boot additional file partition location  */
+#define ENV_SYS_MMC_BOOSCRIPT_PART			1
+#define ENV_SYS_MMC_BOOATENV_PART			1
+/*  rootfs file  */
+#define ENV_SYS_MMC_ROOTFS_PART				2
+#define ENV_ROOT_DEV_ID					0
+
+#define ENV_NUM_VIDEO_OUTPUT				1   /* configurable video output  */
+
+
+#include "seco_mx8_env.h"
+
+#endif /* __SECO_MX8MQ_C25_CONFIG_H */

include/configs/seco_mx8_dtbo.h

@@ -71,4 +71,13 @@
 #define ENV_DTBO_C57_LVDS_DUAL_1920x1080 seco-imx8qxp-c57-lvds-dual-1920x1080.dtbo
 #define ENV_DTBO_C57_EDP                seco-imx8qxp-c57-sn65dsi86-edp.dtbo
 
+#define ENV_DTBO_C25_CAN_RTC		seco-imx8mq-c25-can-rtc.dtbo
+#define ENV_DTBO_C25_DP			seco-imx8mq-c25-dp.dtbo
+#define ENV_DTBO_C25_EDP		seco-imx8mq-c25-edp.dtbo
+#define ENV_DTBO_C25_HDMI		seco-imx8mq-c25-hdmi.dtbo
+#define ENV_DTBO_C25_LVDS_DUAL		seco-imx8mq-c25-lvds-dual.dtbo
+#define ENV_DTBO_C25_PCIE		seco-imx8mq-c25-pcie.dtbo
+#define ENV_DTBO_C25_Q7_SPI		seco-imx8mq-c25-q7-spi.dtbo
+#define ENV_DTBO_C25_UART4		seco-imx8mq-c25-uart4.dtbo
+
 #endif   /* __SECO_MX8_DTBO_H  */