Generate M33 container which has sentinel and upower FW used for
dual boot flexspi nor programming.
Add special fspi parameters head for Adesto ATXP032 flash which uses
4 bytes address for fast read

Signed-off-by: Ye Li <ye.li@nxp.com>

To work around a issue in ROM (MROM-2688) image verify that will cause
reset failure. Move the M33 image before the AP image to workaround it.

Signed-off-by: Ye Li <ye.li@nxp.com>

Signed-off-by: Nitin Garg <nitin.garg@nxp.com>

Signed-off-by: Nitin Garg <nitin.garg@nxp.com>

Signed-off-by: Nitin Garg <nitin.garg@nxp.com>

For cockpit targets, not all are dependent on tee.bin

Signed-off-by: Nitin Garg <nitin.garg@nxp.com>

Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>

Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>

Add cockpit support for 2 cluster of i.MX8QM

Signed-off-by: Seb Fagard <sebastien.fagard@nxp.com>
Signed-off-by: Fabrice Goucem <fabrice.goucem@nxp.com>
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

iMX8/8X REV A is deprecated revision hence removing
its support.

Signed-off-by: Nitin Garg <nitin.garg@nxp.com>

On iMX8MQ B2, ROM will check IVT header and requires the reserved fields
in IVT to be 0.
However, in imx-mkimage we set the reserved1 field for the offset from
second boot image to SPL boot image, which was used for mfgtool but
has deprecated. So remove it to fix the boot failure on iMX8MQ B2.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

Cleanup old A0 code and remove iMX8dv.

Signed-off-by: Nitin Garg <nitin.garg@nxp.com>

According to M33 memory layout, adjust M33 image address to SSRAM7 which
is map to M33 code region

Signed-off-by: Ye Li <ye.li@nxp.com>

Add misc targets fior 8QM as needed for unlocking
devices with signed messages.

Signed-off-by: Nitin Garg <nitin.garg@nxp.com>

Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>

Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>

This reverts commit 88d2796f.

Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>

Update the ATF load address to 0x970000 to provide a
continuous OCRAM space for other purpose.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>

DD3L EVK board only has 512MB of DDR.
move OP-TEE mapping for all the 8MN boards.

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>

The build targets in scripts directory also needs update to use
8DXL A1 SECO firmware

Signed-off-by: Ye Li <ye.li@nxp.com>

Change to use mx8dxla1-ahab-container.img as default for A1.
For A0 chip, user has to set the REVISION=A0 in command line.
For example: make SOC=iMX8DXL REVISION=A0 flash

Signed-off-by: Seb Haezebrouck <sebastien.haezebrouck@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>

Set to use 202006 version DDR4 firmware for iMX8MP DDR4 EVK board

Signed-off-by: Ye Li <ye.li@nxp.com>

Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>

Add two build targets flash_ddr3l_evk and flash_ddr3l_evk_flexspi.
For iMX8MN, needs to use DDR3 FW 201810 version

Signed-off-by: Ye Li <ye.li@nxp.com>

Switch to latest 202006 LPDDR4 FW version for iMX8MP.

Signed-off-by: Ye Li <ye.li@nxp.com>

To resolve conflict with M33 code region, BL31 is moved to SSRAM P5/P6.
So update the its default address in imx-mkimage

Signed-off-by: Ye Li <ye.li@nxp.com>

SPL_CMD is used only when SPL included in boot image. However, we
wrongly added it in previous patch to some non-A core targets.

Signed-off-by: Ye Li <ye.li@nxp.com>

Fix wrong ahab image name and V2X dummy address in extended targets.

Signed-off-by: Ye Li <ye.li@nxp.com>

Change the upower FW address from dummy address to a real address
in upower code ram which is supported by latest ROM.

Signed-off-by: Ye Li <ye.li@nxp.com>

Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>

Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>

This implements a tricky way to release more 64KB OCRAM to V2X FW.
Now ROM uses the dummy address to load the V2X FW, however it keeps
the offset between V2X container to V2X FW. Because there is SECO FW
before V2X FW, so there is about 70-80KB OCRAM is wasted.

Due to ROM image array check, we can't overlay the destination address
of the images. So using a tricky method to split the SPL to two images.
First image is loaded as A35 boot image, second is loaded as DATA image.
The SPL is split at V2X OCRAM address, because V2X dummy image is zero size,
this way can pass the ROM image array check.

Signed-off-by: Ye Li <ye.li@nxp.com>

This reverts commit 8d1454ba.

ROM has a overlay check for image array. When set V2X dummy to 0x110000,
its image dst will overlay with SPL's dst + size. Then ROM fails
to boot up.

Signed-off-by: Ye Li <ye.li@nxp.com>

Last version of V2X FW is larger than early ones.
It need more space in OCRAM when this option is chosen instead of DDR.

ROM copies the V2X FW into dummy address at a same offset between
V2X container header to V2X FW. By checking the image, current offset is
0x13c00. It means we could move the dummy address from 0x120000 to 0x10C400
(0x120000 – 0x13c00) at most. With margin added, it should be safe to use
0x110000 and this won't cause conflict with SPL

Signed-off-by: Stéphane Dion <stephane.dion_1@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>

Update uboot and ATF address to match latest codes

Signed-off-by: Ye Li <ye.li@nxp.com>

iMX8ULP also uses container format in ROM but with different addresses
and CORE id definition. Extend the tool to support iMX8ULP, and add some
default build targets.

The addresses of upower and sentinal are provisional and need be finalized.

Signed-off-by: Ye Li <ye.li@nxp.com>

Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>
(cherry picked from commit b0ce6fecdbd7718e6779a97f8f610f4b1d77be25)

Run "./scripts/gen_sit.sh [sect_off]" to generate the secondary image
table (sit.bin), which is padded to 512 bytes.
[sect_off] is the firstSectorNumber field in SIT table.

Signed-off-by: Ye Li <ye.li@nxp.com>

After u-boot upgraded to imx_v2020.04, the imx8mq validation board
is renamed to val not arm2. Update the new name in build script

Signed-off-by: Ye Li <ye.li@nxp.com>