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Commit 4352f717 authored by Peng Fan's avatar Peng Fan
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iMX8QX: DDR3: switch to use 1066MHz ECC 


Add 1066MHz/933MHz/800MHz ecc script, and default use 1066MHz ECC
script.

Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
(cherry picked from commit f95f0550)
parent 65461ff0
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iMX8QX/imx8qx_ddr3_dcd_1066MHz_ecc.cfg 0 → 100644
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View file @ 4352f717
#define __ASSEMBLY__
#include <ddrc_mem_map.h>
#include <ddr_phy_mem_map.h>
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
#ifndef SCFW_DCD
// Set DRAM clock frequency for the following operation: 1066MHz
DATA 4 0xff190000 0x00000CB1 /* DRC0 bringup */
#else
/* Set the DRC rate to achieve a DRAM rate as close as possible to 1066MHz. */
uint32_t rate2 = 531000000;
pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2);
#endif
DATA 4 0x41C80208 0x1
DATA 4 0x41C80040 0xb // Assert uMCTL2 core reset
DATA 4 0x41C80204 0x1 // Start functional clocks.
/* DRAM 0 controller configuration begin */
DATA 4 DDRC_MSTR_0 0x81040001 // Set DDR3l, BL = 16 and active ranks
DATA 4 DDRC_RFSHTMG_0 0x0082008B // tREFI, tRFC
DATA 4 DDRC_INIT0_0 0x40030106 // pre_cke
DATA 4 DDRC_INIT1_0 0x006A0000 // dram_rstn
DATA 4 DDRC_INIT3_0 0x00240006 // MR0, MR1
DATA 4 DDRC_INIT4_0 0x00280000 // MR2, MR3
DATA 4 DDRC_INIT5_0 0x000C0000 // ZQINIT
DATA 4 DDRC_RANKCTL_0 0x0000072F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
DATA 4 DDRC_DRAMTMG0_0 0x0F132412 // wr2pr, tFAW, tRASmax, tRASmin
DATA 4 DDRC_DRAMTMG1_0 0x000D0419 // tXP, rd2pre, tRC
DATA 4 DDRC_DRAMTMG2_0 0x0507060B // WL, RL, rd2wr, wr2rd
DATA 4 DDRC_DRAMTMG3_0 0x00002008 // T_MOD, T_MRD
DATA 4 DDRC_DRAMTMG4_0 0x07020408 // trcd, tccd, trrd, trp
DATA 4 DDRC_DRAMTMG5_0 0x06060403 // tCKCKEH, tCKCKEL, tckesr, tcke
DATA 4 DDRC_DRAMTMG8_0 0x03030906 // tckdpde, tckdpdx, tckcsx
DATA 4 DDRC_ZQCTL0_0 0x40AB002B // tZQCAL, tZQLAT
DATA 4 DDRC_ZQCTL1_0 0x02000083 // tZQReset, tzq_short_interval
DATA 4 DDRC_DFITMG0_0 0x048A8207
DATA 4 DDRC_DFITMG1_0 0x00060303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
DATA 4 DDRC_DFITMG2_0 0x00000805
DATA 4 DDRC_DFIMISC_0 0x00000001 // dfi_data_cs_polarity
DATA 4 DDRC_DFIUPD0_0 0xE0400018 // Disable the automatic dfi_ctrlupd_req generation
DATA 4 DDRC_DFIUPD1_0 0x001A0057 // dfi_ctrlupd_req generation interval generation (min and max)
DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en
DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0
DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6
DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated
DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
DATA 4 DDRC_ADDRMAP6_0 0x0F070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12
DATA 4 DDRC_ECCCFG0_0 0x044FFFC4 // ecc support (uncommented when ECC is enabled)
DATA 4 DDRC_ODTCFG_0 0x06000610
DATA 4 DDRC_ODTMAP_0 0x00000001 // rank[3:0]_wr_odt, rank[3:0]_wr_odt
DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0
DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000
DATA 4 DDRC_PWRCTL_0 0x00000000
DATA 4 0x41c80208 0x1
DATA 4 0x41c80040 0xf
DATA 4 0x41c80204 0x1
//-------------------------------------------
// Configure registers for PHY initialization
// Timings are computed for 1066MHz DRAM operation
//--------------------------------------------
// Set-up DRAM Configuration Register
DATA 4 DDR_PHY_DCR_0 0x0000040B // DDR3 selection with 8 bank
// Set-up byte and bit swapping registers
DATA 4 DDR_PHY_DX0DQMAP0_0 0x00071628 // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004053 // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_DX1DQMAP0_0 0x00073826 // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004150 // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053608 // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004271 // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053826 // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004170 // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_DX4DQMAP0_0 0x00005281 // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX4DQMAP1_0 0x00004736 // DQ bit 5/6/7 and DM remapping
// Set-up PHY General Configuration Register
// PGCR1,4,5,6,7 are untouched
SET_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=1 (no uMCTL2 commands can go to memory)
DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // Set ADCP=1 (Address Copy)
DATA 4 DDR_PHY_PGCR2_0 0x00F1024C // Set tREFPRD
DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity
// Set-up PHY Timing Register
// PTR2 is untouched
DATA 4 DDR_PHY_PTR0_0 0x42C21550 // tPLLPD, tPLLGS, tPHYRST
DATA 4 DDR_PHY_PTR1_0 0x340F12BE // tPLLLOCK, tPLLRST
// Set-up PLL Control Register
DATA 4 DDR_PHY_PLLCR0_0 0x011C0000
DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x011C0000
// Set-up Impedance Control Register
DATA 4 DDR_PHY_ZQCR_0 0x008A2858 // Set ODT_MODE=0b10(DDR3 stype pullup)
// ZPROG_DRAM_ODT and ZPROG_HOST_ODT
DATA 4 DDR_PHY_ZQ0PR0_0 0x77BB // Optimal setting based on factory testing
DATA 4 DDR_PHY_ZQ1PR0_0 0x77BB // Optimal setting based on factory testing
// Set-up PHY Initialization Register
DATA 4 DDR_PHY_PIR_0 0x72
// Launch initialization (set bit 0)
DATA 4 DDR_PHY_PIR_0 0x73
//-------------------------------------------
// Configure registers for DRAM initialization
//-------------------------------------------
// Set-up Mode Register
// MR0, MR3, MR4, MR5 MR6 are untouched
DATA 4 DDR_PHY_MR0_0 0x00000024
DATA 4 DDR_PHY_MR1_0 0x00000006
DATA 4 DDR_PHY_MR2_0 0x00000028
DATA 4 DDR_PHY_MR3_0 0x00000000
// Set-up DRAM Timing Parameters Register
// DTPR6 is untouched
DATA 4 DDR_PHY_DTPR0_0 0x07240E08 // tRRD, tRAS, tRP, tRTP
DATA 4 DDR_PHY_DTPR1_0 0x28260400 // tWLMRD, tFAW, tODTUP, tMRD
DATA 4 DDR_PHY_DTPR2_0 0x01060200 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
DATA 4 DDR_PHY_DTPR3_0 0x02000000 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
DATA 4 DDR_PHY_DTPR4_0 0x01160C1A // tRFC, tWLO, tXP
DATA 4 DDR_PHY_DTPR5_0 0x00320E09 // tRC, tRCD, tWTR
// Set-up PHY Timing Register
DATA 4 DDR_PHY_PTR3_0 0x0008223A // tDINIT0
DATA 4 DDR_PHY_PTR4_0 0x00000116 // tDINIT1
DATA 4 DDR_PHY_PTR5_0 0x000340E4 // tDINIT2
DATA 4 DDR_PHY_PTR6_0 0x0400042C // tDINIT4, tDINIT3
// Set-up ODT Configuration Register
// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write
DATA 4 DDR_PHY_ODTCR_0 0x00010000 // ODT of rank1 disabled
// Set-up AC I/O Configuration Register
// ACIOCR1-4 are untouched
DATA 4 DDR_PHY_ACIOCR0_0 0x30070400 // PNUM2 (i.e.DDR3) selection [10:11] = 0x2
DATA 4 DDR_PHY_ACIOCR5_0 0x00000000 // I/O mode = DDR3
DATA 4 DDR_PHY_IOVCR0_0 0x03000000
// Set-up DATX8 General Configuration Registers
// DXnGCR0-4 are untouched
DATA 4 DDR_PHY_PGCR5_0 0x01010004
// Set-up DATX8 General Configuration Registers
DATA 4 DDR_PHY_DX0GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX1GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX2GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX3GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX4GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX0GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4 DDR_PHY_DX1GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4 DDR_PHY_DX2GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4 DDR_PHY_DX3GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4 DDR_PHY_DX4GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
// Set-up DATX8 DX Control Register 2
// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA
DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400
// Set-up DATX8 IO Control Register
DATA 4 DDR_PHY_DX8SLbIOCR_0 0x00000000 // I/O mode = DDR3
#if DDR_TRAIN_IN_DCD
// Wait PHY initialization end then launch DRAM initialization
// Wait for bit 0 of PGSR0 to be '1'
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured
// Launch DRAM 0 initialization (set bit 0)
DATA 4 DDR_PHY_PIR_0 0x180
DATA 4 DDR_PHY_PIR_0 0x181
// DRAM 0 initialization end
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
//---------------------------------------------------------------//
// DATA training
//---------------------------------------------------------------//
// Set-up Data Training Configuration Register
// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys
// case 9001045655: Design limitation in DDR3 mode: REFRESH must be disabled during DQS2DQ training).
// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED).
DATA 4 DDR_PHY_DTCR0_0 0x800031CF // Set DTRPTN to 0x7. RFSHDT=0
DATA 4 DDR_PHY_DTCR1_0 0x00010237 // Set RANKEN=3
// CLR_BIT 4 DDR_PHY_DX4GCR1_0 0xFF // disable byte 4 (this line is commented out when ECC is enabled)
// Launch Write leveling
DATA 4 DDR_PHY_PIR_0 0x200
DATA 4 DDR_PHY_PIR_0 0x201
// Wait Write leveling to complete
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000
// Set DQS/DQSn glitch suppression resistor for training PHY0
DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7
// Launch Read DQS training
DATA 4 DDR_PHY_PIR_0 0x400
DATA 4 DDR_PHY_PIR_0 0x401
// Wait Read DQS training to complete PHY0
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000
// Remove DQS/DQSn glitch suppression resistor PHY0
DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000
// DQS2DQ training, Write leveling, Deskew and eye trainings
DATA 4 DDR_PHY_PIR_0 0x0000F800
DATA 4 DDR_PHY_PIR_0 0x0000F801
// Wait for training to complete
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
//Re-allow uMCTL2 to send commands to DDR
CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=0, PUBMODE=0
//Check that controller is ready to operate
CHECK_BITS_SET 4 DDRC_STAT_0 0x1
#endif
// ECC Support (the following lines are uncommented when ECC is enabled)
DATA 4 DDRC_PCTRL_0_0 0x00000000 // Disable Port 0
DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_mode = 1
DATA 4 DDRC_SBRWDATA0_0 0x55AA55AA // SBRWDATA0 = 55AA55AA
DATA 4 DDRC_SBRCTL_0 0x00000015 // Scrub_en = 1
CHECK_BITS_SET 4 DDRC_SBRSTAT_0 0x2 // Wait for Scrub done
CHECK_BITS_CLR 4 DDRC_SBRSTAT_0 0x1 // Wait for Scrub done
DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_en = 0
DATA 4 DDRC_SBRCTL_0 0x00000110 // Scrub_interval = 1
DATA 4 DDRC_SBRCTL_0 0x00000111 // Scrub_en = 1
DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable Port 0
iMX8QX/imx8qx_ddr3_dcd_800MHz_ecc.cfg 0 → 100644
+ 243
− 0
View file @ 4352f717
#define __ASSEMBLY__
#include <ddrc_mem_map.h>
#include <ddr_phy_mem_map.h>
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
#ifndef SCFW_DCD
// Set DRAM clock frequency for the following operation: 800MHz
DATA 4 0xff190000 0x00000C85 /* DRC0 bringup */
#else
/* Set the DRC rate to achieve a DRAM rate as close as possible to 800MHz. */
uint32_t rate2 = SC_400MHz;
pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2);
#endif
DATA 4 0x41C80208 0x1
DATA 4 0x41C80040 0xb // Assert uMCTL2 core reset
DATA 4 0x41C80204 0x1 // Start functional clocks.
/* DRAM 0 controller configuration begin */
DATA 4 DDRC_MSTR_0 0x81040001 // Set DDR3l, BL = 16 and active ranks
DATA 4 DDRC_RFSHTMG_0 0x00620068 // tREFI, tRFC
DATA 4 DDRC_INIT0_0 0x400300C5 // pre_cke
DATA 4 DDRC_INIT1_0 0x00500000 // dram_rstn
DATA 4 DDRC_INIT3_0 0x00700006 // MR0, MR1
DATA 4 DDRC_INIT4_0 0x00180000 // MR2, MR3
DATA 4 DDRC_INIT5_0 0x00090000 // ZQINIT
DATA 4 DDRC_RANKCTL_0 0x0000072F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
DATA 4 DDRC_DRAMTMG0_0 0x0C0E1B0E // wr2pr, tFAW, tRASmax, tRASmin
DATA 4 DDRC_DRAMTMG1_0 0x000A0313 // tXP, rd2pre, tRC
DATA 4 DDRC_DRAMTMG2_0 0x04060609 // WL, RL, rd2wr, wr2rd
DATA 4 DDRC_DRAMTMG3_0 0x00002006 // T_MOD, T_MRD
DATA 4 DDRC_DRAMTMG4_0 0x06020306 // trcd, tccd, trrd, trp
DATA 4 DDRC_DRAMTMG5_0 0x04040403 // tCKCKEH, tCKCKEL, tckesr, tcke
DATA 4 DDRC_DRAMTMG8_0 0x03030905 // tckdpde, tckdpdx, tckcsx
DATA 4 DDRC_ZQCTL0_0 0x40800020 // tZQCAL, tZQLAT
DATA 4 DDRC_ZQCTL1_0 0x02000062 // tZQReset, tzq_short_interval
DATA 4 DDRC_DFITMG0_0 0x04878205
DATA 4 DDRC_DFITMG1_0 0x00060303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
DATA 4 DDRC_DFITMG2_0 0x00000503
DATA 4 DDRC_DFIMISC_0 0x00000001 // dfi_data_cs_polarity
DATA 4 DDRC_DFIUPD0_0 0xE0400018 // Disable the automatic dfi_ctrlupd_req generation
DATA 4 DDRC_DFIUPD1_0 0x001A0057 // dfi_ctrlupd_req generation interval generation (min and max)
DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en
DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0
DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6
DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated
DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
DATA 4 DDRC_ADDRMAP6_0 0x0F070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12
DATA 4 DDRC_ECCCFG0_0 0x044FFFC4 // ecc support (uncommented when ECC is enabled)
DATA 4 DDRC_ODTCFG_0 0x06000610
DATA 4 DDRC_ODTMAP_0 0x00000001 // rank[3:0]_wr_odt, rank[3:0]_wr_odt
DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0
DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000
DATA 4 DDRC_PWRCTL_0 0x00000000
DATA 4 0x41c80208 0x1
DATA 4 0x41c80040 0xf
DATA 4 0x41c80204 0x1
//-------------------------------------------
// Configure registers for PHY initialization
// Timings are computed for 800MHz DRAM operation
//--------------------------------------------
// Set-up DRAM Configuration Register
DATA 4 DDR_PHY_DCR_0 0x0000040B // DDR3 selection with 8 bank
// Set-up byte and bit swapping registers
DATA 4 DDR_PHY_DX0DQMAP0_0 0x00071628 // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004053 // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_DX1DQMAP0_0 0x00073826 // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004150 // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053608 // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004271 // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053826 // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004170 // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_DX4DQMAP0_0 0x00005281 // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX4DQMAP1_0 0x00004736 // DQ bit 5/6/7 and DM remapping
// Set-up PHY General Configuration Register
// PGCR1,4,5,6,7 are untouched
SET_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=1 (no uMCTL2 commands can go to memory)
DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // Set ADCP=1 (Address Copy)
DATA 4 DDR_PHY_PGCR2_0 0x00F0C170 // Set tREFPRD
DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity
// Set-up PHY Timing Register
// PTR2 is untouched
DATA 4 DDR_PHY_PTR0_0 0x32019010 // tPLLPD, tPLLGS, tPHYRST
DATA 4 DDR_PHY_PTR1_0 0x27100E10 // tPLLLOCK, tPLLRST
// Set-up PLL Control Register
DATA 4 DDR_PHY_PLLCR0_0 0x011C0000
DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x011C0000
// Set-up Impedance Control Register
DATA 4 DDR_PHY_ZQCR_0 0x008A2858 // Set ODT_MODE=0b10(DDR3 stype pullup)
// ZPROG_DRAM_ODT and ZPROG_HOST_ODT
DATA 4 DDR_PHY_ZQ0PR0_0 0x77BB // Optimal setting based on factory testing
DATA 4 DDR_PHY_ZQ1PR0_0 0x77BB // Optimal setting based on factory testing
// Set-up PHY Initialization Register
DATA 4 DDR_PHY_PIR_0 0x72
// Launch initialization (set bit 0)
DATA 4 DDR_PHY_PIR_0 0x73
//-------------------------------------------
// Configure registers for DRAM initialization
//-------------------------------------------
// Set-up Mode Register
// MR0, MR3, MR4, MR5 MR6 are untouched
DATA 4 DDR_PHY_MR0_0 0x00000070
DATA 4 DDR_PHY_MR1_0 0x00000006
DATA 4 DDR_PHY_MR2_0 0x00000018
DATA 4 DDR_PHY_MR3_0 0x00000000
// Set-up DRAM Timing Parameters Register
// DTPR6 is untouched
DATA 4 DDR_PHY_DTPR0_0 0x051B0B06 // tRRD, tRAS, tRP, tRTP
DATA 4 DDR_PHY_DTPR1_0 0x281C0000 // tWLMRD, tFAW, tODTUP, tMRD
DATA 4 DDR_PHY_DTPR2_0 0x01060200 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
DATA 4 DDR_PHY_DTPR3_0 0x02000000 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
DATA 4 DDR_PHY_DTPR4_0 0x00D00C14 // tRFC, tWLO, tXP
DATA 4 DDR_PHY_DTPR5_0 0x00250B07 // tRC, tRCD, tWTR
// Set-up PHY Timing Register
DATA 4 DDR_PHY_PTR3_0 0x00061A80 // tDINIT0
DATA 4 DDR_PHY_PTR4_0 0x000000D0 // tDINIT1
DATA 4 DDR_PHY_PTR5_0 0x00027100 // tDINIT2
DATA 4 DDR_PHY_PTR6_0 0x04000321 // tDINIT4, tDINIT3
// Set-up ODT Configuration Register
// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write
DATA 4 DDR_PHY_ODTCR_0 0x00010000 // ODT of rank1 disabled
// Set-up AC I/O Configuration Register
// ACIOCR1-4 are untouched
DATA 4 DDR_PHY_ACIOCR0_0 0x30070400 // PNUM2 (i.e.DDR3) selection [10:11] = 0x2
DATA 4 DDR_PHY_ACIOCR5_0 0x00000000 // I/O mode = DDR3
DATA 4 DDR_PHY_IOVCR0_0 0x03000000
// Set-up DATX8 General Configuration Registers
// DXnGCR0-4 are untouched
DATA 4 DDR_PHY_PGCR5_0 0x01010004
// Set-up DATX8 General Configuration Registers
DATA 4 DDR_PHY_DX0GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX1GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX2GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX3GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX4GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX0GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4 DDR_PHY_DX1GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4 DDR_PHY_DX2GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4 DDR_PHY_DX3GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4 DDR_PHY_DX4GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
// Set-up DATX8 DX Control Register 2
// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA
DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400
// Set-up DATX8 IO Control Register
DATA 4 DDR_PHY_DX8SLbIOCR_0 0x00000000 // I/O mode = DDR3
#if DDR_TRAIN_IN_DCD
// Wait PHY initialization end then launch DRAM initialization
// Wait for bit 0 of PGSR0 to be '1'
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured
// Launch DRAM 0 initialization (set bit 0)
DATA 4 DDR_PHY_PIR_0 0x180
DATA 4 DDR_PHY_PIR_0 0x181
// DRAM 0 initialization end
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
//---------------------------------------------------------------//
// DATA training
//---------------------------------------------------------------//
// Set-up Data Training Configuration Register
// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys
// case 9001045655: Design limitation in DDR3 mode: REFRESH must be disabled during DQS2DQ training).
// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED).
DATA 4 DDR_PHY_DTCR0_0 0x800031CF // Set DTRPTN to 0x7. RFSHDT=0
DATA 4 DDR_PHY_DTCR1_0 0x00010237 // Set RANKEN=3
// CLR_BIT 4 DDR_PHY_DX4GCR1_0 0xFF // disable byte 4 (this line is commented out when ECC is enabled)
// Launch Write leveling
DATA 4 DDR_PHY_PIR_0 0x200
DATA 4 DDR_PHY_PIR_0 0x201
// Wait Write leveling to complete
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000
// Set DQS/DQSn glitch suppression resistor for training PHY0
DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7
// Launch Read DQS training
DATA 4 DDR_PHY_PIR_0 0x400
DATA 4 DDR_PHY_PIR_0 0x401
// Wait Read DQS training to complete PHY0
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000
// Remove DQS/DQSn glitch suppression resistor PHY0
DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000
// DQS2DQ training, Write leveling, Deskew and eye trainings
DATA 4 DDR_PHY_PIR_0 0x0000F800
DATA 4 DDR_PHY_PIR_0 0x0000F801
// Wait for training to complete
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
//Re-allow uMCTL2 to send commands to DDR
CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=0, PUBMODE=0
//Check that controller is ready to operate
CHECK_BITS_SET 4 DDRC_STAT_0 0x1
#endif
// ECC Support (the following lines are uncommented when ECC is enabled)
DATA 4 DDRC_PCTRL_0_0 0x00000000 // Disable Port 0
DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_mode = 1
DATA 4 DDRC_SBRWDATA0_0 0x55AA55AA // SBRWDATA0 = 55AA55AA
DATA 4 DDRC_SBRCTL_0 0x00000015 // Scrub_en = 1
CHECK_BITS_SET 4 DDRC_SBRSTAT_0 0x2 // Wait for Scrub done
CHECK_BITS_CLR 4 DDRC_SBRSTAT_0 0x1 // Wait for Scrub done
DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_en = 0
DATA 4 DDRC_SBRCTL_0 0x00000110 // Scrub_interval = 1
DATA 4 DDRC_SBRCTL_0 0x00000111 // Scrub_en = 1
DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable Port 0
iMX8QX/imx8qx_ddr3_dcd_933MHz_ecc.cfg 0 → 100644
+ 243
− 0
View file @ 4352f717
#define __ASSEMBLY__
#include <ddrc_mem_map.h>
#include <ddr_phy_mem_map.h>
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
#ifndef SCFW_DCD
// Set DRAM clock frequency for the following operation: 933MHz
DATA 4 0xff190000 0x00000C9B /* DRC0 bringup */
#else
/* Set the DRC rate to achieve a DRAM rate as close as possible to 933MHz. */
uint32_t rate2 = 465000000;
pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2);
#endif
DATA 4 0x41C80208 0x1
DATA 4 0x41C80040 0xb // Assert uMCTL2 core reset
DATA 4 0x41C80204 0x1 // Start functional clocks.
/* DRAM 0 controller configuration begin */
DATA 4 DDRC_MSTR_0 0x81040001 // Set DDR3l, BL = 16 and active ranks
DATA 4 DDRC_RFSHTMG_0 0x0072007A // tREFI, tRFC
DATA 4 DDRC_INIT0_0 0x400300E5 // pre_cke
DATA 4 DDRC_INIT1_0 0x005D0000 // dram_rstn
DATA 4 DDRC_INIT3_0 0x00140006 // MR0, MR1
DATA 4 DDRC_INIT4_0 0x00200000 // MR2, MR3
DATA 4 DDRC_INIT5_0 0x000B0000 // ZQINIT
DATA 4 DDRC_RANKCTL_0 0x0000072F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
DATA 4 DDRC_DRAMTMG0_0 0x0E112010 // wr2pr, tFAW, tRASmax, tRASmin
DATA 4 DDRC_DRAMTMG1_0 0x000C0416 // tXP, rd2pre, tRC
DATA 4 DDRC_DRAMTMG2_0 0x0507060B // WL, RL, rd2wr, wr2rd
DATA 4 DDRC_DRAMTMG3_0 0x00002008 // T_MOD, T_MRD
DATA 4 DDRC_DRAMTMG4_0 0x07020307 // trcd, tccd, trrd, trp
DATA 4 DDRC_DRAMTMG5_0 0x05050403 // tCKCKEH, tCKCKEL, tckesr, tcke
DATA 4 DDRC_DRAMTMG8_0 0x03030905 // tckdpde, tckdpdx, tckcsx
DATA 4 DDRC_ZQCTL0_0 0x40960026 // tZQCAL, tZQLAT
DATA 4 DDRC_ZQCTL1_0 0x02000072 // tZQReset, tzq_short_interval
DATA 4 DDRC_DFITMG0_0 0x04898206
DATA 4 DDRC_DFITMG1_0 0x00060303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
DATA 4 DDRC_DFITMG2_0 0x00000704
DATA 4 DDRC_DFIMISC_0 0x00000001 // dfi_data_cs_polarity
DATA 4 DDRC_DFIUPD0_0 0xE0400018 // Disable the automatic dfi_ctrlupd_req generation
DATA 4 DDRC_DFIUPD1_0 0x001A0057 // dfi_ctrlupd_req generation interval generation (min and max)
DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en
DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0
DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6
DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated
DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
DATA 4 DDRC_ADDRMAP6_0 0x0F070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12
DATA 4 DDRC_ECCCFG0_0 0x044FFFC4 // ecc support (uncommented when ECC is enabled)
DATA 4 DDRC_ODTCFG_0 0x06000610
DATA 4 DDRC_ODTMAP_0 0x00000001 // rank[3:0]_wr_odt, rank[3:0]_wr_odt
DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0
DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000
DATA 4 DDRC_PWRCTL_0 0x00000000
DATA 4 0x41c80208 0x1
DATA 4 0x41c80040 0xf
DATA 4 0x41c80204 0x1
//-------------------------------------------
// Configure registers for PHY initialization
// Timings are computed for 933MHz DRAM operation
//--------------------------------------------
// Set-up DRAM Configuration Register
DATA 4 DDR_PHY_DCR_0 0x0000040B // DDR3 selection with 8 bank
// Set-up byte and bit swapping registers
DATA 4 DDR_PHY_DX0DQMAP0_0 0x00071628 // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004053 // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_DX1DQMAP0_0 0x00073826 // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004150 // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053608 // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004271 // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053826 // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004170 // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_DX4DQMAP0_0 0x00005281 // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX4DQMAP1_0 0x00004736 // DQ bit 5/6/7 and DM remapping
// Set-up PHY General Configuration Register
// PGCR1,4,5,6,7 are untouched
SET_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=1 (no uMCTL2 commands can go to memory)
DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // Set ADCP=1 (Address Copy)
DATA 4 DDR_PHY_PGCR2_0 0x00F0E207 // Set tREFPRD
DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity
// Set-up PHY Timing Register
// PTR2 is untouched
DATA 4 DDR_PHY_PTR0_0 0x3A61D310 // tPLLPD, tPLLGS, tPHYRST
DATA 4 DDR_PHY_PTR1_0 0x2D98106A // tPLLLOCK, tPLLRST
// Set-up PLL Control Register
DATA 4 DDR_PHY_PLLCR0_0 0x011C0000
DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x011C0000
// Set-up Impedance Control Register
DATA 4 DDR_PHY_ZQCR_0 0x008A2858 // Set ODT_MODE=0b10(DDR3 stype pullup)
// ZPROG_DRAM_ODT and ZPROG_HOST_ODT
DATA 4 DDR_PHY_ZQ0PR0_0 0x77BB // Optimal setting based on factory testing
DATA 4 DDR_PHY_ZQ1PR0_0 0x77BB // Optimal setting based on factory testing
// Set-up PHY Initialization Register
DATA 4 DDR_PHY_PIR_0 0x72
// Launch initialization (set bit 0)
DATA 4 DDR_PHY_PIR_0 0x73
//-------------------------------------------
// Configure registers for DRAM initialization
//-------------------------------------------
// Set-up Mode Register
// MR0, MR3, MR4, MR5 MR6 are untouched
DATA 4 DDR_PHY_MR0_0 0x00000014
DATA 4 DDR_PHY_MR1_0 0x00000006
DATA 4 DDR_PHY_MR2_0 0x00000020
DATA 4 DDR_PHY_MR3_0 0x00000000
// Set-up DRAM Timing Parameters Register
// DTPR6 is untouched
DATA 4 DDR_PHY_DTPR0_0 0x061F0D08 // tRRD, tRAS, tRP, tRTP
DATA 4 DDR_PHY_DTPR1_0 0x28210300 // tWLMRD, tFAW, tODTUP, tMRD
DATA 4 DDR_PHY_DTPR2_0 0x01060200 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
DATA 4 DDR_PHY_DTPR3_0 0x02000000 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
DATA 4 DDR_PHY_DTPR4_0 0x00F30C17 // tRFC, tWLO, tXP
DATA 4 DDR_PHY_DTPR5_0 0x002C0D09 // tRC, tRCD, tWTR
// Set-up PHY Timing Register
DATA 4 DDR_PHY_PTR3_0 0x00071FA6 // tDINIT0
DATA 4 DDR_PHY_PTR4_0 0x000000F3 // tDINIT1
DATA 4 DDR_PHY_PTR5_0 0x0002D976 // tDINIT2
DATA 4 DDR_PHY_PTR6_0 0x040003A7 // tDINIT4, tDINIT3
// Set-up ODT Configuration Register
// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write
DATA 4 DDR_PHY_ODTCR_0 0x00010000 // ODT of rank1 disabled
// Set-up AC I/O Configuration Register
// ACIOCR1-4 are untouched
DATA 4 DDR_PHY_ACIOCR0_0 0x30070400 // PNUM2 (i.e.DDR3) selection [10:11] = 0x2
DATA 4 DDR_PHY_ACIOCR5_0 0x00000000 // I/O mode = DDR3
DATA 4 DDR_PHY_IOVCR0_0 0x03000000
// Set-up DATX8 General Configuration Registers
// DXnGCR0-4 are untouched
DATA 4 DDR_PHY_PGCR5_0 0x01010004
// Set-up DATX8 General Configuration Registers
DATA 4 DDR_PHY_DX0GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX1GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX2GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX3GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX4GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX0GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4 DDR_PHY_DX1GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4 DDR_PHY_DX2GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4 DDR_PHY_DX3GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4 DDR_PHY_DX4GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
// Set-up DATX8 DX Control Register 2
// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA
DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400
// Set-up DATX8 IO Control Register
DATA 4 DDR_PHY_DX8SLbIOCR_0 0x00000000 // I/O mode = DDR3
#if DDR_TRAIN_IN_DCD
// Wait PHY initialization end then launch DRAM initialization
// Wait for bit 0 of PGSR0 to be '1'
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured
// Launch DRAM 0 initialization (set bit 0)
DATA 4 DDR_PHY_PIR_0 0x180
DATA 4 DDR_PHY_PIR_0 0x181
// DRAM 0 initialization end
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
//---------------------------------------------------------------//
// DATA training
//---------------------------------------------------------------//
// Set-up Data Training Configuration Register
// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys
// case 9001045655: Design limitation in DDR3 mode: REFRESH must be disabled during DQS2DQ training).
// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED).
DATA 4 DDR_PHY_DTCR0_0 0x800031CF // Set DTRPTN to 0x7. RFSHDT=0
DATA 4 DDR_PHY_DTCR1_0 0x00010237 // Set RANKEN=3
// CLR_BIT 4 DDR_PHY_DX4GCR1_0 0xFF // disable byte 4 (this line is commented out when ECC is enabled)
// Launch Write leveling
DATA 4 DDR_PHY_PIR_0 0x200
DATA 4 DDR_PHY_PIR_0 0x201
// Wait Write leveling to complete
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000
// Set DQS/DQSn glitch suppression resistor for training PHY0
DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7
// Launch Read DQS training
DATA 4 DDR_PHY_PIR_0 0x400
DATA 4 DDR_PHY_PIR_0 0x401
// Wait Read DQS training to complete PHY0
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000
// Remove DQS/DQSn glitch suppression resistor PHY0
DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000
// DQS2DQ training, Write leveling, Deskew and eye trainings
DATA 4 DDR_PHY_PIR_0 0x0000F800
DATA 4 DDR_PHY_PIR_0 0x0000F801
// Wait for training to complete
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000
//Re-allow uMCTL2 to send commands to DDR
CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=0, PUBMODE=0
//Check that controller is ready to operate
CHECK_BITS_SET 4 DDRC_STAT_0 0x1
#endif
// ECC Support (the following lines are uncommented when ECC is enabled)
DATA 4 DDRC_PCTRL_0_0 0x00000000 // Disable Port 0
DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_mode = 1
DATA 4 DDRC_SBRWDATA0_0 0x55AA55AA // SBRWDATA0 = 55AA55AA
DATA 4 DDRC_SBRCTL_0 0x00000015 // Scrub_en = 1
CHECK_BITS_SET 4 DDRC_SBRSTAT_0 0x2 // Wait for Scrub done
CHECK_BITS_CLR 4 DDRC_SBRSTAT_0 0x1 // Wait for Scrub done
DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_en = 0
DATA 4 DDRC_SBRCTL_0 0x00000110 // Scrub_interval = 1
DATA 4 DDRC_SBRCTL_0 0x00000111 // Scrub_en = 1
DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable Port 0
iMX8QX/soc.mak
+ 3
− 3
View file @ 4352f717
......@@ -5,8 +5,8 @@ DCD_CFG = imx8qx_dcd.cfg.tmp
DCD_CFG_16BIT_SRC = imx8qx_dcd_16bit_1.2GHz.cfg
DCD_16BIT_CFG = imx8qx_16bit_dcd.cfg.tmp
DCD_CFG_DDR3_SRC = imx8qx_ddr3_dcd_933MHz.cfg
DCD_DDR3_CFG = imx8qx_ddr3_dcd_933MHz.cfg.tmp
DCD_CFG_DDR3_SRC = imx8qx_ddr3_dcd_1066MHz_ecc.cfg
DCD_DDR3_CFG = imx8qx_ddr3_dcd_1066MHz_ecc.cfg.tmp
CC ?= gcc
CFLAGS ?= -O2 -Wall -std=c99 -static
......@@ -22,7 +22,7 @@ SERVER=http://yb2.am.freescale.net
DIR = build-output/Linux_IMX_MX8/$(N)/common_bsp
ifeq ($(DDR3_DCD), 1)
DCD_CFG_SRC = imx8qx_ddr3_dcd_933MHz.cfg
DCD_CFG_SRC = imx8qx_ddr3_dcd_1066MHz_ecc.cfg
endif
ifneq ($(wildcard /usr/bin/rename.ul),)
......
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