[DRIVER] clk: imx: pll1443x: add PLL SSCG support

In some situations, users might face EMI issues due to spikes around specific frequencies: enabling Spread Spectrum Clocking is indicated to reduce the electromagnetic peak around that specific frequency.

From the i.MX8MP SoC Reference Manual document, Section 5.1.8 "CCM Analog Memory Map/Register Definition", the DRAM PLL, Audio PLL1, Audio PLL2 and Video PLL1 have available the spread spectrum function.

The spread spectrum mode parameters of these PLLs can be calculated using the formulas below:

• Modulation frequency: MF = Fin / p / mfr / (2^5) [Hz]
• Modulation rate: MR = mfr * mrr / m / (2^6) × 100 [%: percentage of the PLL output frequency]
• Where:
  • 0 ≤ mfr ≤ 255, 1 ≤ mrr ≤ 63, 0 ≤ mrr × mfr ≤ 512
  • Fin - PLL input clock frequency (typically, 24MHz = 24 * (10^6) Hz)
  • p = CCM_ANALOG_XXX_YYY_FDIV_CTL0[PLL_PRE_DIV] - reference frequency pre-divider value
  • m = CCM_ANALOG_XXX_YYY_FDIV_CTL0[PLL_MAIN_DIV] - PLL main divider value
  • mfr = CCM_ANALOG_XXX_YYY_SSCG_CTRL[PLL_MFREQ_CTL] - modulation frequency factor
  • mrr = CCM_ANALOG_XXX_YYY_SSCG_CTRL[PLL_MRAT_CTL] - modulation range factor